118 lines
4.2 KiB
Scala
118 lines
4.2 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.chip
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import Chisel._
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import freechips.rocketchip.config._
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import freechips.rocketchip.devices.debug._
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import freechips.rocketchip.devices.tilelink._
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import freechips.rocketchip.coreplex._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.jtag.JTAGIO
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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/** All the traits defined in this file assume that they are being mixed in
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* to a system that has a standard RISCV-based coreplex platform.
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*/
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trait HasCoreplexRISCVPlatform {
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implicit val p: Parameters
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val coreplex: CoreplexRISCVPlatform
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}
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/** A wrapper around JTAG providing a reset signal and manufacturer id. */
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class SystemJTAGIO extends Bundle {
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val jtag = new JTAGIO(hasTRSTn = false).flip
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val reset = Bool(INPUT)
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val mfr_id = UInt(INPUT, 11)
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}
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/** A wrapper bundle containing one of the two possible debug interfaces */
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class DebugIO(implicit p: Parameters) extends ParameterizedBundle()(p) {
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val clockeddmi = (!p(IncludeJtagDTM)).option(new ClockedDMIIO().flip)
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val systemjtag = (p(IncludeJtagDTM)).option(new SystemJTAGIO)
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val ndreset = Bool(OUTPUT)
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val dmactive = Bool(OUTPUT)
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}
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/** Either adds a JTAG DTM to system, and exports a JTAG interface,
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* or exports the Debug Module Interface (DMI), based on a global parameter.
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*/
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trait HasPeripheryDebug extends HasSystemNetworks with HasCoreplexRISCVPlatform {
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val module: HasPeripheryDebugModuleImp
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}
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trait HasPeripheryDebugBundle extends HasPeripheryParameters {
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val debug: DebugIO
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def connectDebug(c: Clock, r: Bool, out: Bool) {
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debug.clockeddmi.foreach { d =>
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val dtm = Module(new SimDTM).connect(c, r, d, out)
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}
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debug.systemjtag.foreach { sj =>
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val jtag = Module(new JTAGVPI).connect(sj.jtag, sj.reset, r, out)
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sj.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
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}
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}
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}
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trait HasPeripheryDebugModuleImp extends LazyMultiIOModuleImp with HasPeripheryDebugBundle {
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val outer: HasPeripheryDebug
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val debug = IO(new DebugIO)
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debug.clockeddmi.foreach { dbg => outer.coreplex.module.io.debug <> dbg }
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val dtm = debug.systemjtag.map { sj =>
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val dtm = Module(new DebugTransportModuleJTAG(p(DMKey).nDMIAddrSize, p(JtagDTMKey)))
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dtm.io.jtag <> sj.jtag
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dtm.clock := sj.jtag.TCK
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dtm.io.jtag_reset := sj.reset
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dtm.io.jtag_mfr_id := sj.mfr_id
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dtm.reset := dtm.io.fsmReset
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outer.coreplex.module.io.debug.dmi <> dtm.io.dmi
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outer.coreplex.module.io.debug.dmiClock := sj.jtag.TCK
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outer.coreplex.module.io.debug.dmiReset := ResetCatchAndSync(sj.jtag.TCK, sj.reset, "dmiResetCatch")
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dtm
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}
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debug.ndreset := outer.coreplex.module.io.ndreset
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debug.dmactive := outer.coreplex.module.io.dmactive
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}
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/** Real-time clock is based on RTCPeriod relative to system clock.
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* Note: nothing about this is diplomatic, all the work is done in the ModuleImp
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*/
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trait HasPeripheryRTCCounter extends HasSystemNetworks with HasCoreplexRISCVPlatform {
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val module: HasPeripheryRTCCounterModuleImp
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}
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trait HasPeripheryRTCCounterModuleImp extends LazyMultiIOModuleImp {
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val outer: HasPeripheryRTCCounter
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val period = p(RTCPeriod)
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val rtcCounter = RegInit(UInt(0, width = log2Up(period)))
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val rtcWrap = rtcCounter === UInt(period-1)
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rtcCounter := Mux(rtcWrap, UInt(0), rtcCounter + UInt(1))
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outer.coreplex.module.io.rtcToggle := rtcCounter(log2Up(period)-1)
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}
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/** Adds a boot ROM that contains the DTB describing the system's coreplex. */
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trait HasPeripheryBootROM extends HasSystemNetworks with HasCoreplexRISCVPlatform {
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val bootrom_address = 0x10000
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val bootrom_size = 0x10000
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val bootrom_hang = 0x10040
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private lazy val bootrom_contents = GenerateBootROM(coreplex.dtb)
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val bootrom = LazyModule(new TLROM(bootrom_address, bootrom_size, bootrom_contents, true, peripheryBusConfig.beatBytes))
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bootrom.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
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}
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/** Coreplex will power-on running at 0x10040 (BootROM) */
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trait HasPeripheryBootROMModuleImp extends LazyMultiIOModuleImp {
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val outer: HasPeripheryBootROM
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outer.coreplex.module.io.resetVector := UInt(outer.bootrom_hang)
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}
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