4c595d175c
* Refactors package hierarchy. Additionally: - Removes legacy ground tests and configs - Removes legacy bus protocol implementations - Removes NTiles - Adds devices package - Adds more functions to util package
115 lines
4.5 KiB
Scala
115 lines
4.5 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.amba.ahb
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import Chisel._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.regmapper._
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import freechips.rocketchip.tilelink.{IntSourceNode, IntSourcePortSimple}
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import freechips.rocketchip.util.{HeterogeneousBag, MaskGen}
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import scala.math.{min,max}
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class AHBRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)
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extends AHBSlaveNode(Seq(AHBSlavePortParameters(
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Seq(AHBSlaveParameters(
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address = Seq(address),
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executable = executable,
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supportsWrite = TransferSizes(1, min(address.alignment.toInt, beatBytes * AHBParameters.maxTransfer)),
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supportsRead = TransferSizes(1, min(address.alignment.toInt, beatBytes * AHBParameters.maxTransfer)))),
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beatBytes = beatBytes)))
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{
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require (address.contiguous)
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// Calling this method causes the matching AHB bundle to be
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// configured to route all requests to the listed RegFields.
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def regmap(mapping: RegField.Map*) = {
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val ahb = bundleIn(0)
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val indexBits = log2Up((address.mask+1)/beatBytes)
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val params = RegMapperParams(indexBits, beatBytes, 1)
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val in = Wire(Decoupled(new RegMapperInput(params)))
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val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*)
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val d_phase = RegInit(Bool(false))
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val d_taken = Reg(Bool())
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val d_read = Reg(Bool())
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val d_index = Reg(UInt(width = indexBits))
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val d_mask = Reg(UInt(width = beatBytes))
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// Only send the request to the RR once
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d_taken := d_phase && in.ready
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in.valid := d_phase && !d_taken
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in.bits.read := d_read
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in.bits.index := d_index
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in.bits.data := ahb.hwdata
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in.bits.mask := d_mask
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in.bits.extra := UInt(0)
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when (ahb.hready) { d_phase := Bool(false) }
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ahb.hreadyout := !d_phase || out.valid
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ahb.hresp := AHBParameters.RESP_OKAY
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ahb.hrdata := out.bits.data
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val request = ahb.htrans === AHBParameters.TRANS_NONSEQ || ahb.htrans === AHBParameters.TRANS_SEQ
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when (ahb.hready && ahb.hsel && request) {
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assert (!in.valid || in.ready)
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d_phase := Bool(true)
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d_taken := Bool(false)
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d_read := !ahb.hwrite
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d_index := ahb.haddr >> log2Ceil(beatBytes)
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d_mask := MaskGen(ahb.haddr, ahb.hsize, beatBytes)
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}
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out.ready := Bool(true)
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assert (d_phase || !out.valid)
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}
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}
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object AHBRegisterNode
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{
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def apply(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false) =
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new AHBRegisterNode(address, concurrency, beatBytes, undefZero, executable)
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}
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// These convenience methods below combine to make it possible to create a AHB
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// register mapped device from a totally abstract register mapped device.
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abstract class AHBRegisterRouterBase(address: AddressSet, interrupts: Int, concurrency: Int, beatBytes: Int, undefZero: Boolean, executable: Boolean)(implicit p: Parameters) extends LazyModule
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{
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val node = AHBRegisterNode(address, concurrency, beatBytes, undefZero, executable)
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val intnode = IntSourceNode(IntSourcePortSimple(num = interrupts))
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}
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case class AHBRegBundleArg(interrupts: HeterogeneousBag[Vec[Bool]], in: HeterogeneousBag[AHBBundle])(implicit val p: Parameters)
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class AHBRegBundleBase(arg: AHBRegBundleArg) extends Bundle
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{
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implicit val p = arg.p
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val interrupts = arg.interrupts
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val in = arg.in
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}
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class AHBRegBundle[P](val params: P, arg: AHBRegBundleArg) extends AHBRegBundleBase(arg)
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class AHBRegModule[P, B <: AHBRegBundleBase](val params: P, bundleBuilder: => B, router: AHBRegisterRouterBase)
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extends LazyModuleImp(router) with HasRegMap
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{
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val io = bundleBuilder
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val interrupts = if (io.interrupts.isEmpty) Vec(0, Bool()) else io.interrupts(0)
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def regmap(mapping: RegField.Map*) = router.node.regmap(mapping:_*)
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}
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class AHBRegisterRouter[B <: AHBRegBundleBase, M <: LazyModuleImp]
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(val base: BigInt, val interrupts: Int = 0, val size: BigInt = 4096, val concurrency: Int = 0, val beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)
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(bundleBuilder: AHBRegBundleArg => B)
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(moduleBuilder: (=> B, AHBRegisterRouterBase) => M)(implicit p: Parameters)
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extends AHBRegisterRouterBase(AddressSet(base, size-1), interrupts, concurrency, beatBytes, undefZero, executable)
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{
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require (isPow2(size))
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// require (size >= 4096) ... not absolutely required, but highly recommended
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lazy val module = moduleBuilder(bundleBuilder(AHBRegBundleArg(intnode.bundleOut, node.bundleIn)), this)
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}
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