c5838dd9b3
Until recently, we were assuming that the data channel in AXI was always right-justified. However, for narrow writes, the data must actually be aligned within the byte lanes. This commit changes some of the converters in order to fix this issue. There was a bug in the L2 cache in which a merged get request was causing the tracker to read the old data from the data array, overwriting the updated data acquired from outer memory. Changed it so that pending_reads is no longer set if the data in the buffer is already valid. There was a bug in the PortedTileLinkCrossbar. The new GrantFromSrc and FinishToDst types used client_id for routing to managers. This caused bits to get cut off, which meant the Finish messages could not be routed correctly. Changed to use manager_id instead.
148 lines
3.1 KiB
C++
148 lines
3.1 KiB
C++
// See LICENSE for license details.
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#include "mm.h"
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#include <iostream>
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#include <fstream>
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#include <cstdlib>
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#include <cstring>
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#include <cassert>
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void mm_t::write(uint64_t addr, uint8_t *data, uint64_t strb, uint64_t size)
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{
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strb &= ((1 << size) - 1) << (addr % word_size);
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if (addr > this->size) {
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fprintf(stderr, "Invalid write address %lx\n", addr);
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exit(EXIT_FAILURE);
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}
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uint8_t *base = this->data + (addr / word_size) * word_size;
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for (int i = 0; i < word_size; i++) {
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if (strb & 1)
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base[i] = data[i];
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strb >>= 1;
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}
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}
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std::vector<char> mm_t::read(uint64_t addr)
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{
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if (addr > this->size) {
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fprintf(stderr, "Invalid read address %lx\n", addr);
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exit(EXIT_FAILURE);
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}
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uint8_t *base = this->data + addr;
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return std::vector<char>(base, base + word_size);
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}
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void mm_t::init(size_t sz, int wsz, int lsz)
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{
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assert(wsz > 0 && lsz > 0 && (lsz & (lsz-1)) == 0 && lsz % wsz == 0);
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word_size = wsz;
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line_size = lsz;
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data = new uint8_t[sz];
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size = sz;
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}
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mm_t::~mm_t()
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{
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delete [] data;
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}
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void mm_magic_t::init(size_t sz, int wsz, int lsz)
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{
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mm_t::init(sz, wsz, lsz);
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dummy_data.resize(word_size);
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}
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void mm_magic_t::tick(
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bool ar_valid,
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uint64_t ar_addr,
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uint64_t ar_id,
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uint64_t ar_size,
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uint64_t ar_len,
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bool aw_valid,
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uint64_t aw_addr,
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uint64_t aw_id,
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uint64_t aw_size,
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uint64_t aw_len,
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bool w_valid,
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uint64_t w_strb,
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void *w_data,
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bool w_last,
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bool r_ready,
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bool b_ready)
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{
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bool ar_fire = ar_valid && ar_ready();
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bool aw_fire = aw_valid && aw_ready();
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bool w_fire = w_valid && w_ready();
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bool r_fire = r_valid() && r_ready;
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bool b_fire = b_valid() && b_ready;
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if (ar_fire) {
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uint64_t start_addr = (ar_addr / word_size) * word_size;
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for (int i = 0; i <= ar_len; i++) {
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auto dat = read(start_addr + i * word_size);
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rresp.push(mm_rresp_t(ar_id, dat, i == ar_len));
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}
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}
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if (aw_fire) {
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store_addr = aw_addr;
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store_id = aw_id;
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store_count = aw_len + 1;
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store_size = 1 << aw_size;
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store_inflight = true;
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}
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if (w_fire) {
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write(store_addr, (uint8_t *) w_data, w_strb, store_size);
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store_addr += store_size;
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store_count--;
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if (store_count == 0) {
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store_inflight = false;
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bresp.push(store_id);
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assert(w_last);
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}
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}
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if (b_fire)
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bresp.pop();
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if (r_fire)
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rresp.pop();
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cycle++;
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}
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void load_mem(void** mems, const char* fn, int line_size, int nchannels)
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{
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char* m;
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ssize_t start = 0;
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std::ifstream in(fn);
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if (!in)
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{
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std::cerr << "could not open " << fn << std::endl;
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exit(-1);
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}
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std::string line;
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while (std::getline(in, line))
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{
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#define parse_nibble(c) ((c) >= 'a' ? (c)-'a'+10 : (c)-'0')
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for (ssize_t i = line.length()-2, j = 0; i >= 0; i -= 2, j++) {
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char data = (parse_nibble(line[i]) << 4) | parse_nibble(line[i+1]);
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ssize_t addr = start + j;
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int channel = (addr / line_size) % nchannels;
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m = (char *) mems[channel];
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addr = (addr / line_size / nchannels) * line_size + (addr % line_size);
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m[addr] = data;
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}
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start += line.length()/2;
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}
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}
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