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rocket-chip/csrc
Howard Mao c5838dd9b3 Fix narrow read/write behavior for AXI converters and fix L2 bugs
Until recently, we were assuming that the data channel in AXI was always
right-justified. However, for narrow writes, the data must actually be
aligned within the byte lanes. This commit changes some of the
converters in order to fix this issue.

There was a bug in the L2 cache in which a merged get request was
causing the tracker to read the old data from the data array,
overwriting the updated data acquired from outer memory. Changed it so
that pending_reads is no longer set if the data in the buffer is already
valid.

There was a bug in the PortedTileLinkCrossbar. The new GrantFromSrc and
FinishToDst types used client_id for routing to managers. This caused
bits to get cut off, which meant the Finish messages could not be routed
correctly. Changed to use manager_id instead.
2016-04-12 15:39:15 -07:00
..
comlog.cc cleaner/faster comlog without linear search 2015-09-15 17:19:29 -07:00
emulator.cc add option to print cycle count regardless of exit status 2015-12-04 12:04:13 -08:00
float_fix.cc remove bugs from float_fix 2015-09-23 16:11:47 -07:00
htif_emulator.h Support SCR address generation with __OFFSET at the end 2016-02-25 21:57:37 -08:00
mm_dramsim2.cc Fix narrow read/write behavior for AXI converters and fix L2 bugs 2016-04-12 15:39:15 -07:00
mm_dramsim2.h Fix narrow read/write behavior for AXI converters and fix L2 bugs 2016-04-12 15:39:15 -07:00
mm.cc Fix narrow read/write behavior for AXI converters and fix L2 bugs 2016-04-12 15:39:15 -07:00
mm.h Fix narrow read/write behavior for AXI converters and fix L2 bugs 2016-04-12 15:39:15 -07:00
vcs_main.rocketTestHarness.cc Allow the number of memory channels to be picked at runtime 2016-02-17 15:23:30 -08:00
vcs_main.ZscaleTestHarness.cc Fix zscale testing 2015-12-01 17:31:48 -08:00