.. |
Arbiter.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
AsyncCrossing.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
AtomicAutomata.scala
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tilelink: fix AtomicAutomata bug wrt early source reuse
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2017-07-26 12:52:29 -07:00 |
Atomics.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
Broadcast.scala
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tilelink: remove obsolete addr_lo signal (#895)
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2017-07-26 16:01:21 -07:00 |
Buffer.scala
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tilelink Buffer: use new :=? adapter API
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2017-09-07 16:03:35 -07:00 |
Bundles.scala
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tilelink: remove obsolete addr_lo signal (#895)
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2017-07-26 16:01:21 -07:00 |
Bus.scala
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tilelink Bus: toAsyncSlaves now supports BufferChains
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2017-09-07 16:03:35 -07:00 |
CacheCork.scala
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tilelink: CacheCork uses constructor helpers
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2017-07-27 18:38:15 -07:00 |
Delayer.scala
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tilelink: remove obsolete addr_lo signal (#895)
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2017-07-26 16:01:21 -07:00 |
Edges.scala
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tilelink: remove obsolete addr_lo signal (#895)
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2017-07-26 16:01:21 -07:00 |
Example.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
FIFOFixer.scala
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tileink: FIFOFixer should cope with zero-latency devices
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2017-07-19 19:38:27 -07:00 |
Filter.scala
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tilelink: Filter, add another case
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2017-07-31 16:51:26 -07:00 |
Fragmenter.scala
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tilelink: remove obsolete addr_lo signal (#895)
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2017-07-26 16:01:21 -07:00 |
Fuzzer.scala
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TLFuzzer: Correct the number of ordered clients created
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2017-08-02 15:48:21 -07:00 |
HintHandler.scala
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tilelink: remove obsolete addr_lo signal (#895)
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2017-07-26 16:01:21 -07:00 |
IntNodes.scala
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syncregs: Use synchronizer primitives for IntXing
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2017-08-24 17:39:07 -07:00 |
Isolation.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
Map.scala
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tilelink: add TLMap to make it possible to move slaves
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2017-07-31 16:39:00 -07:00 |
Metadata.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
Monitor.scala
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tilelink: use the Monitor to enforce Probe sourcing
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2017-07-28 18:08:00 -07:00 |
NodeNumberer.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
Nodes.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
package.scala
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Combine Coreplex and System Module Hierarchies (#875)
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2017-07-23 08:31:04 -07:00 |
Parameters.scala
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tilelink: it is now legal to support Acquire for UNCACHED regions
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2017-07-27 11:11:22 -07:00 |
PatternPusher.scala
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PatternPusher: can now expect a certain output (#952)
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2017-08-11 18:10:27 -07:00 |
RAMModel.scala
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tilelink: RAMModel must support source reuse
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2017-08-07 16:01:15 -07:00 |
RationalCrossing.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
RegisterRouter.scala
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tilelink: remove obsolete addr_lo signal (#895)
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2017-07-26 16:01:21 -07:00 |
RegisterRouterTest.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
SourceShrinker.scala
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tilelink: SourceShrinker should work also for 0 latency
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2017-07-26 12:37:31 -07:00 |
Splitter.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
SRAM.scala
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tilelink: remove obsolete addr_lo signal (#895)
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2017-07-26 16:01:21 -07:00 |
ToAHB.scala
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tilelink: remove obsolete addr_lo signal (#895)
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2017-07-26 16:01:21 -07:00 |
ToAPB.scala
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tilelink: remove obsolete addr_lo signal (#895)
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2017-07-26 16:01:21 -07:00 |
ToAXI4.scala
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tilelink: remove obsolete addr_lo signal (#895)
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2017-07-26 16:01:21 -07:00 |
WidthWidget.scala
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tilelink: cut WidthWidget from dependency on addr_lo
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2017-07-26 10:31:09 -07:00 |
Xbar.scala
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TLXbar: Allow more masters and slaves and issue a warning.
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2017-08-03 15:46:06 -07:00 |