133 lines
4.1 KiB
Scala
133 lines
4.1 KiB
Scala
package rocket
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import Chisel._
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import hwacha._
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import uncore.constants.MemoryOpConstants._
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import Util._
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class RocketIO(implicit conf: RocketConfiguration) extends Bundle
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{
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val host = new HTIFIO(conf.tl.ln.nClients)
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val imem = new CPUFrontendIO()(conf.icache)
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val vimem = new CPUFrontendIO()(conf.icache)
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val dmem = new HellaCacheIO()(conf.dcache)
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}
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class Core(implicit conf: RocketConfiguration) extends Component
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{
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val io = new RocketIO
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val ctrl = new Control
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val dpath = new Datapath
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ctrl.io.dpath <> dpath.io.ctrl
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dpath.io.host <> io.host
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ctrl.io.imem <> io.imem
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dpath.io.imem <> io.imem
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val dmemArb = new HellaCacheArbiter(2 + conf.vec)
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dmemArb.io.mem <> io.dmem
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val dmem = dmemArb.io.requestor
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dmem(1) <> ctrl.io.dmem
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dmem(1) <> dpath.io.dmem
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val ptw = collection.mutable.ArrayBuffer(io.imem.ptw, io.dmem.ptw)
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val fpu: FPU = if (conf.fpu) {
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val fpu = new FPU(4,6)
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dpath.io.fpu <> fpu.io.dpath
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ctrl.io.fpu <> fpu.io.ctrl
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fpu
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} else null
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if (conf.vec) {
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val vu = new vu(Reg(reset))
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val vdtlb = new TLB(8)
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ptw += vdtlb.io.ptw
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vdtlb.io <> vu.io.vtlb
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val pftlb = new TLB(2)
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pftlb.io <> vu.io.vpftlb
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ptw += pftlb.io.ptw
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dpath.io.vec_ctrl <> ctrl.io.vec_dpath
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// hooking up vector I$
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ptw += io.vimem.ptw
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io.vimem.req.bits.pc := vu.io.imem_req.bits
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io.vimem.req.valid := vu.io.imem_req.valid
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io.vimem.invalidate := ctrl.io.imem.invalidate
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vu.io.imem_resp.valid := io.vimem.resp.valid
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vu.io.imem_resp.bits.pc := io.vimem.resp.bits.pc
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vu.io.imem_resp.bits.data := io.vimem.resp.bits.data
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vu.io.imem_resp.bits.xcpt_ma := io.vimem.resp.bits.xcpt_ma
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vu.io.imem_resp.bits.xcpt_if := io.vimem.resp.bits.xcpt_if
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io.vimem.resp.ready := vu.io.imem_resp.ready
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io.vimem.req.bits.mispredict := Bool(false)
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io.vimem.req.bits.taken := Bool(false)
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ctrl.io.vec_iface.vcmdq <> vu.io.vcmdq
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ctrl.io.vec_iface.vximm1q <> vu.io.vximm1q
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ctrl.io.vec_iface.vximm2q <> vu.io.vximm2q
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ctrl.io.vec_iface.vcntq <> vu.io.vcntq
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dpath.io.vec_iface.vcmdq <> vu.io.vcmdq
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dpath.io.vec_iface.vximm1q <> vu.io.vximm1q
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dpath.io.vec_iface.vximm2q <> vu.io.vximm2q
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dpath.io.vec_iface.vcntq <> vu.io.vcntq
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ctrl.io.vec_iface.vpfcmdq <> vu.io.vpfcmdq
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ctrl.io.vec_iface.vpfximm1q <> vu.io.vpfximm1q
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ctrl.io.vec_iface.vpfximm2q <> vu.io.vpfximm2q
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ctrl.io.vec_iface.vpfcntq <> vu.io.vpfcntq
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dpath.io.vec_iface.vpfcmdq <> vu.io.vpfcmdq
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dpath.io.vec_iface.vpfximm1q <> vu.io.vpfximm1q
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dpath.io.vec_iface.vpfximm2q <> vu.io.vpfximm2q
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dpath.io.vec_iface.vpfcntq <> vu.io.vpfcntq
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// user level vector command queue ready signals
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ctrl.io.vec_iface.vcmdq_user_ready := vu.io.vcmdq_user_ready
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ctrl.io.vec_iface.vximm1q_user_ready := vu.io.vximm1q_user_ready
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ctrl.io.vec_iface.vximm2q_user_ready := vu.io.vximm2q_user_ready
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// fences
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ctrl.io.vec_iface.vfence_ready := vu.io.vfence_ready
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// irqs
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ctrl.io.vec_iface.irq := vu.io.irq
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ctrl.io.vec_iface.irq_cause := vu.io.irq_cause
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dpath.io.vec_iface.irq_aux := vu.io.irq_aux
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// exceptions
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vu.io.xcpt.exception := ctrl.io.vec_iface.exception
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vu.io.xcpt.evac := ctrl.io.vec_iface.evac
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vu.io.xcpt.evac_addr := dpath.io.vec_iface.evac_addr.toUFix
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vu.io.xcpt.kill := ctrl.io.vec_iface.kill
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vu.io.xcpt.hold := ctrl.io.vec_iface.hold
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// hooking up vector memory interface
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dmem(2).req.bits.data := RegEn(StoreGen(vu.io.dmem_req.bits).data, vu.io.dmem_req.valid && isWrite(vu.io.dmem_req.bits.cmd))
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dmem(2).req <> vu.io.dmem_req
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dmem(2).resp <> vu.io.dmem_resp
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// DON'T share vector integer multiplier with rocket
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vu.io.cp_imul_req.valid := Bool(false)
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// share sfma and dfma pipelines with rocket
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require(conf.fpu)
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fpu.io.sfma <> vu.io.cp_sfma
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fpu.io.dfma <> vu.io.cp_dfma
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} else if (conf.fpu) {
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fpu.io.sfma.valid := Bool(false)
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fpu.io.dfma.valid := Bool(false)
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}
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val thePTW = new PTW(ptw.length)
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ptw zip thePTW.io.requestor map { case (a, b) => a <> b }
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thePTW.io.dpath <> dpath.io.ptw
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dmem(0) <> thePTW.io.mem
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}
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