Megan Wachs e82328336e Add in a SimJTAG to connect to OpenOCD's remote-bitbang interface. ... This is simpler than JTAGVPI and is supported better by Verilor. It is also the same thing Spike uses.		2018-01-05 16:02:52 -08:00
..
AsyncResetReg.v	async_reset_reg: Don't randomize the register if rst is asserted anyway	2017-09-20 14:47:00 -07:00
ClockDivider2.v	ClockDivider: add docs to appease the reviewer	2017-02-17 19:35:08 +01:00
ClockDivider3.v	vsrc: add ClockDivider3 used to simulate unaligned clocks	2017-05-14 15:05:55 -07:00
jtag_vpi.tab	JTAG VPI: Make it work without debug_pp flag	2017-05-30 15:46:45 -07:00
jtag_vpi.v	jtag_vpi: Use a parameter for INIT_DELAY vs constant	2017-09-07 09:06:07 -07:00
plusarg_reader.v	Fix omitted parameter (#1014)	2017-09-25 14:11:28 -07:00
SimDTM.v	debug: Fixes in how the SimDTM was hooked up to FESVR	2017-03-28 21:13:45 -07:00
SimJTAG.v	Add in a SimJTAG to connect to OpenOCD's remote-bitbang interface.	2018-01-05 16:02:52 -08:00
TestDriver.v	Add +dump-start=N option to VCS	2017-04-20 17:00:46 -07:00