rocket-chip/src/main/scala at 42f1ae27fc35378456db5b8f18e1b22f938b6bfd - rocket-chip - Tiband Gitea

riscv/rocket-chip

Files

T

History

Wesley W. Terpstra 42f1ae27fc Xbar: use the IdentityModule to encourage wider fanout

2017-09-07 16:03:35 -07:00

..

tilelink: Error device supports Acquire

2017-07-27 18:32:58 -07:00

config: support p.lift(key) to optionally return a value

2017-09-07 16:03:34 -07:00

coreplex: add externalSlaveBuffers configuration option

2017-09-07 16:03:35 -07:00

plic: support a configurable number of interrupt register stages

2017-09-07 16:03:34 -07:00

diplomacy: support :=? for unknown star inference

2017-09-07 16:03:35 -07:00

chiplink: adjust bus view to include the splitter (#886 )

2017-07-24 21:41:17 -07:00

Jtagresettobool - add explicit toBool cast now required on reset. (#984 )

2017-09-06 09:49:47 -07:00

add cloneType to RegisterWriteIO and RegisterReadIO (#874 )

2017-07-18 18:52:31 -07:00

Remove redundant check in interrupt priority encoding

2017-08-17 22:23:42 -07:00

tilelink: add mask rom

2017-07-31 21:34:04 -07:00

coreplex: add externalSlaveBuffers configuration option

2017-09-07 16:03:35 -07:00

Xbar: use the IdentityModule to encourage wider fanout

2017-09-07 16:03:35 -07:00

Combine Coreplex and System Module Hierarchies (#875 )

2017-07-23 08:31:04 -07:00

util: add the IdentityModule, useful to dedup wires

2017-09-07 16:03:35 -07:00