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rocket-chip/src/main/scala
Albert Huntington 7fc8337cdb
Merge pull request #1180 from freechipsproject/addrwregdesc
Allow rwReg to pass name and description to RegField for documentation.
2018-01-08 09:44:44 -08:00
..
amba Error device: require explicit control of atomic and transfer sizes 2017-12-08 13:41:09 -08:00
config config: fix warning 2017-09-22 14:58:36 -07:00
coreplex coreplex: fix TL MMIO port example 2018-01-05 12:29:47 +01:00
devices Make ErrorDevice UNCACHEABLE instead of UNCACHED 2018-01-05 14:00:42 -08:00
diplomacy tile: BaseTile refactor, pt 1 2017-12-26 11:04:15 -08:00
groundtest tile: BaseTileModule => BaseTileModuleImp 2018-01-02 17:55:54 -08:00
interrupts diplomacy: provide a val name for all LazyModule constructions 2017-12-01 11:28:21 -08:00
jtag JTAG: Revert to Chisel._ for Issue 1160 (#1161) 2017-12-18 21:02:31 -08:00
regmapper Allow rwReg to pass name and description to RegField for documentation. 2018-01-05 16:59:58 -08:00
rocket Reduce cases in which FENCE.I must flush D$ 2018-01-05 13:58:14 -08:00
system coreplex: WithStatelessBridge => WithIncoherentTiles (#1092) 2017-11-07 13:47:56 -08:00
tile tile: BaseTileModule => BaseTileModuleImp 2018-01-02 17:55:54 -08:00
tilelink Make ErrorDevice UNCACHEABLE instead of UNCACHED 2018-01-05 14:00:42 -08:00
unittest unittest: add an API for describing LazyModule unit tests 2017-12-01 11:26:59 -08:00
util Add Cross Cover Property Library (#1149) 2017-12-07 18:46:10 -08:00