09e29e8fe0
only supports generating Verilog, which plugs into the fpga-spartan6 repository, for now
25 lines
698 B
Plaintext
25 lines
698 B
Plaintext
[submodule "uncore"]
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path = uncore
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url = https://github.com/ucb-bar/uncore.git
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[submodule "dramsim2"]
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path = dramsim2
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url = https://github.com/dramninjasUMD/DRAMSim2.git
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[submodule "riscv-tools"]
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path = riscv-tools
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url = https://github.com/ucb-bar/riscv-tools.git
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[submodule "rocket"]
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path = rocket
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url = https://github.com/ucb-bar/rocket.git
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[submodule "chisel"]
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path = chisel
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url = https://github.com/ucb-bar/chisel.git
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[submodule "hardfloat"]
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path = hardfloat
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url = https://github.com/ucb-bar/berkeley-hardfloat.git
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[submodule "fpga-zynq"]
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path = fpga-zynq
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url = https://github.com/ucb-bar/fpga-zynq.git
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[submodule "zscale"]
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path = zscale
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url = https://github.com/ucb-bar/zscale
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