111 lines
2.8 KiB
Scala
111 lines
2.8 KiB
Scala
// See LICENSE for license details.
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package uncore
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import Chisel._
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object MuxBundle {
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def apply[T <: Data] (default: T, mapping: Seq[(Bool, T)]): T = {
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mapping.reverse.foldLeft(default)((b, a) => Mux(a._1, a._2, b))
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}
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def apply[T <: Data] (key: UInt, default: T, mapping: Seq[(UInt, T)]): T = {
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apply(default, mapping.map{ case (a, b) => (a === key, b) })
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}
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}
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// Produces 0-width value when counting to 1
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class ZCounter(val n: Int) {
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val value = Reg(init=UInt(0, log2Ceil(n)))
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def inc(): Bool = {
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if (n == 1) Bool(true)
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else {
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val wrap = value === UInt(n-1)
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value := Mux(Bool(!isPow2(n)) && wrap, UInt(0), value + UInt(1))
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wrap
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}
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}
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}
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object ZCounter {
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def apply(n: Int) = new ZCounter(n)
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def apply(cond: Bool, n: Int): (UInt, Bool) = {
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val c = new ZCounter(n)
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var wrap: Bool = null
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when (cond) { wrap = c.inc() }
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(c.value, cond && wrap)
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}
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}
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object TwoWayCounter {
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def apply(up: Bool, down: Bool, max: Int): UInt = {
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val cnt = Reg(init = UInt(0, log2Up(max+1)))
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when (up && !down) { cnt := cnt + UInt(1) }
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when (down && !up) { cnt := cnt - UInt(1) }
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cnt
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}
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}
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class FlowThroughSerializer[T <: Bundle with HasTileLinkData](gen: T, n: Int) extends Module {
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val io = new Bundle {
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val in = Decoupled(gen).flip
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val out = Decoupled(gen)
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val cnt = UInt(OUTPUT, log2Up(n))
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val done = Bool(OUTPUT)
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}
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val narrowWidth = io.in.bits.data.getWidth / n
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require(io.in.bits.data.getWidth % narrowWidth == 0)
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if(n == 1) {
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io.out <> io.in
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io.cnt := UInt(0)
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io.done := Bool(true)
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} else {
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val cnt = Reg(init=UInt(0, width = log2Up(n)))
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val wrap = cnt === UInt(n-1)
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val rbits = Reg{io.in.bits}
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val active = Reg(init=Bool(false))
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val shifter = Wire(Vec(n, Bits(width = narrowWidth)))
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(0 until n).foreach {
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i => shifter(i) := rbits.data((i+1)*narrowWidth-1,i*narrowWidth)
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}
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io.done := Bool(false)
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io.cnt := cnt
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io.in.ready := !active
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io.out.valid := active || io.in.valid
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io.out.bits := io.in.bits
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when(!active && io.in.valid) {
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when(io.in.bits.hasData()) {
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cnt := Mux(io.out.ready, UInt(1), UInt(0))
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rbits := io.in.bits
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active := Bool(true)
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}
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io.done := !io.in.bits.hasData()
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}
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when(active) {
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io.out.bits := rbits
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io.out.bits.data := shifter(cnt)
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when(io.out.ready) {
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cnt := cnt + UInt(1)
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when(wrap) {
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cnt := UInt(0)
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io.done := Bool(true)
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active := Bool(false)
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}
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}
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}
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}
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}
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object FlowThroughSerializer {
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def apply[T <: Bundle with HasTileLinkData](in: DecoupledIO[T], n: Int): DecoupledIO[T] = {
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val fs = Module(new FlowThroughSerializer(in.bits, n))
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fs.io.in.valid := in.valid
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fs.io.in.bits := in.bits
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in.ready := fs.io.in.ready
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fs.io.out
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}
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}
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