251 lines
5.7 KiB
Scala
251 lines
5.7 KiB
Scala
package rocket
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import Chisel._
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import Node._
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import scala.math._
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object foldR
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{
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def apply[T <: Bits](x: Seq[T])(f: (T, T) => T): T =
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if (x.length == 1) x(0) else f(x(0), foldR(x.slice(1, x.length))(f))
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}
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object log2up
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{
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def apply(in: Int) = if (in == 1) 1 else ceil(log(in)/log(2)).toInt
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}
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object ispow2
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{
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def apply(in: Int) = in > 0 && ((in & (in-1)) == 0)
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}
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object FillInterleaved
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{
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def apply(n: Int, in: Bits) =
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{
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var out = Fill(n, in(0))
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for (i <- 1 until in.getWidth)
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out = Cat(Fill(n, in(i)), out)
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out
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}
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}
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// http://aggregate.ee.engr.uky.edu/MAGIC/#Population%20Count%20%28Ones%20Count%29
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// http://bits.stephan-brumme.com/countBits.html
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object PopCount
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{
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def apply(in: Bits) =
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{
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require(in.width <= 32)
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val w = log2up(in.width+1)
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var x = in
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if(in.width == 2) {
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x = x - ((x >> UFix(1)) & Bits("h_5555_5555"))
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} else if(in.width <= 4) {
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x = x - ((x >> UFix(1)) & Bits("h_5555_5555"))
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x = (((x >> UFix(2)) & Bits("h_3333_3333")) + (x & Bits("h_3333_3333")))
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} else if(in.width <= 8) {
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x = x - ((x >> UFix(1)) & Bits("h_5555_5555"))
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x = (((x >> UFix(2)) & Bits("h_3333_3333")) + (x & Bits("h_3333_3333")))
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x = ((x >> UFix(4)) + x)
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} else {
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// count bits of each 2-bit chunk
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x = x - ((x >> UFix(1)) & Bits("h_5555_5555"))
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// count bits of each 4-bit chunk
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x = (((x >> UFix(2)) & Bits("h_3333_3333")) + (x & Bits("h_3333_3333")))
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// count bits of each 8-bit chunk
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x = ((x >> UFix(4)) + x)
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// mask junk in upper bits
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x = x & Bits("h_0f0f_0f0f")
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// add all four 8-bit chunks
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x = x + (x >> UFix(8))
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x = x + (x >> UFix(16))
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}
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x(w-1,0)
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}
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}
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object Reverse
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{
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def apply(in: Bits) =
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{
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var out = in(in.getWidth-1)
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for (i <- 1 until in.getWidth)
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out = Cat(in(in.getWidth-i-1), out)
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out
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}
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}
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object OHToUFix
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{
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def apply(in: Bits): UFix =
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{
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val out = MuxCase( UFix(0), (0 until in.getWidth).map( i => (in(i).toBool, UFix(i))))
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out.toUFix
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}
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}
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object UFixToOH
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{
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def apply(in: UFix, width: Int): Bits =
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{
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(UFix(1) << in(log2up(width)-1,0))
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}
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}
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object LFSR16
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{
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def apply(increment: Bool = Bool(true)) =
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{
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val width = 16
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val lfsr = Reg(resetVal = UFix(1, width))
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when (increment) { lfsr := Cat(lfsr(0)^lfsr(2)^lfsr(3)^lfsr(5), lfsr(width-1,1)).toUFix }
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lfsr
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}
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}
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object ShiftRegister
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{
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def apply [T <: Data](n: Int, in: T): T =
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if (n > 0) Reg(apply(n-1, in)) else in
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}
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object Mux1H
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{
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//TODO: cloning in(0) is unsafe if other elements have different widths, but
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//is that even allowable?
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def apply [T <: Data](n: Int, sel: Vec[Bool], in: Vec[T]): T = {
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MuxCase(in(0), (0 until n).map( i => (sel(i), in(i))))
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// val mux = (new Mux1H(n)){ in(0).clone }
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// mux.io.sel <> sel
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// mux.io.in <> in
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// mux.io.out.asInstanceOf[T]
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}
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def apply [T <: Data](n: Int, sel: Seq[Bool], in: Vec[T]): T = {
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MuxCase(in(0), (0 until n).map( i => (sel(i), in(i))))
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// val mux = (new Mux1H(n)){ in(0).clone }
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// for(i <- 0 until n) {
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// mux.io.sel(i) := sel(i)
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// }
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// mux.io.in <> in.asOutput
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// mux.io.out.asInstanceOf[T]
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}
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def apply [T <: Data](n: Int, sel: Bits, in: Vec[T]): T = {
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MuxCase(in(0), (0 until n).map( i => (sel(i).toBool, in(i))))
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// val mux = (new Mux1H(n)){ in(0).clone }
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// for(i <- 0 until n) {
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// mux.io.sel(i) := sel(i).toBool
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// }
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// mux.io.in := in
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// mux.io.out
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}
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}
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class Mux1H [T <: Data](n: Int)(gen: => T) extends Component
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{
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val io = new Bundle {
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val sel = Vec(n) { Bool(dir = INPUT) }
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val in = Vec(n) { gen }.asInput
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val out = gen.asOutput
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}
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if (n > 2) {
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var out = io.in(0).toBits & Fill(gen.getWidth, io.sel(0))
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for (i <- 1 to n-1)
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out = out | (io.in(i).toBits & Fill(gen.getWidth, io.sel(i)))
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io.out := out
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} else if (n == 2) {
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io.out := Mux(io.sel(1), io.in(1), io.in(0))
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} else {
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io.out := io.in(0)
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}
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}
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class ioDecoupled[T <: Data]()(data: => T) extends Bundle
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{
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val valid = Bool(INPUT)
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val ready = Bool(OUTPUT)
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val bits = data.asInput
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}
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class ioArbiter[T <: Data](n: Int)(data: => T) extends Bundle {
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val in = Vec(n) { (new ioDecoupled()) { data } }
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val out = (new ioDecoupled()) { data }.flip()
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}
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class Arbiter[T <: Data](n: Int)(data: => T) extends Component {
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val io = new ioArbiter(n)(data)
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io.in(0).ready := io.out.ready
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for (i <- 1 to n-1) {
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io.in(i).ready := !io.in(i-1).valid && io.in(i-1).ready
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}
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var dout = io.in(n-1).bits
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for (i <- 1 to n-1)
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dout = Mux(io.in(n-1-i).valid, io.in(n-1-i).bits, dout)
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var vout = io.in(0).valid
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for (i <- 1 to n-1)
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vout = vout || io.in(i).valid
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vout <> io.out.valid
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dout <> io.out.bits
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}
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class ioPriorityDecoder(in_width: Int, out_width: Int) extends Bundle
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{
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val in = UFix(in_width, INPUT);
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val out = Bits(out_width, OUTPUT);
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}
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class priorityDecoder(width: Int) extends Component
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{
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val in_width = ceil(log10(width)/log10(2)).toInt;
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val io = new ioPriorityEncoder(in_width, width);
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val l_out = Wire() { Bits() };
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l_out := Bits(0, width);
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for (i <- width-1 to 0 by -1) {
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when (io.in === UFix(i, in_width)) {
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l_out := Bits(1,1) << UFix(i);
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}
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}
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io.out := l_out;
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}
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class ioPriorityEncoder(in_width: Int, out_width: Int) extends Bundle
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{
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val in = Bits(in_width, INPUT);
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val out = UFix(out_width, OUTPUT);
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}
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class priorityEncoder(width: Int) extends Component
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{
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val out_width = ceil(log10(width)/log10(2)).toInt;
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val io = new ioPriorityDecoder(width, out_width);
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val l_out = Wire() { UFix() };
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l_out := UFix(0, out_width);
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for (i <- width-1 to 1 by -1) {
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when (io.in(i).toBool) {
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l_out := UFix(i, out_width);
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}
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}
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io.out := l_out;
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}
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