Colin Schmidt f19d504c88 Use % in makefrag-verilog to prevent double firrtl execution (#452) ... * Use % in makefrag-verilog to prevent double firrtl execution		2016-11-25 01:50:01 -08:00
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.gitignore	Write test harness in Chisel	2016-08-15 23:27:27 -07:00
Makefile	Use PROJECT rather than MODEL in name of binary and generated src files.	2016-09-19 13:23:17 -07:00
Makefrag	Simplify AsyncResetReg	2016-10-08 21:29:40 -07:00
Makefrag-verilog	Use % in makefrag-verilog to prevent double firrtl execution (#452)	2016-11-25 01:50:01 -08:00
vlsi_mem_gen	fix null statement in vsli_mem_gen ala firrtl#264 (#252)	2016-09-07 11:04:36 -07:00