26 lines
542 B
Scala
26 lines
542 B
Scala
package rocketchip
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import Chisel._
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import uncore.tilelink._
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import junctions._
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import cde.Parameters
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class ZynqAdapter(implicit val p: Parameters) extends Module
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with HasTopLevelParameters {
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val adapterParams = p.alterPartial({
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case NastiKey => NastiParameters(
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dataBits = 32,
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addrBits = 32,
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idBits = 12)
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case TLId => "L1toL2"
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})
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val io = new Bundle {
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val nasti = new NastiIO()(adapterParams).flip
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val reset = Bool(OUTPUT)
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}
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require(false, "TODO reimplement using debug port, not HTIF")
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}
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