Logo
Explore Help
Sign In
riscv/rocket-chip
Watch 1
Star 0
Fork 0
Code Releases Activity
Files
385b5d569878d4b76d56ccbf8e890b75cc9911ea
rocket-chip/src/main/scala
T
History
Wesley W. Terpstra 385b5d5698 axi4: default should be GET_EFFECTS
2016-11-14 15:19:39 -08:00
..
coreplex
WIP scala compile and firrtl elaborate; monitor error
2016-11-11 13:07:45 -08:00
diplomacy
tilelink2 Xbar: merge the AddressSets of fractured managers
2016-11-03 22:18:28 -07:00
groundtest
WIP scala compile and firrtl elaborate; monitor error
2016-11-11 13:07:45 -08:00
junctions
rocketchip: all of the address map now comes from TL2
2016-10-31 11:42:44 -07:00
regmapper
regmapper RegisterCrossing: safe AsyncQueues are overkill here
2016-10-14 18:28:31 -07:00
rocket
WIP
2016-11-14 13:39:01 -08:00
rocketchip
axi4: default should be GET_EFFECTS
2016-11-14 15:19:39 -08:00
uncore
axi4: default should be GET_EFFECTS
2016-11-14 15:19:39 -08:00
unittest
diplomacy: print out bus widths on edges in agent graph
2016-10-31 11:42:47 -07:00
util
WIP uncore and rocket changes compile
2016-11-10 15:57:29 -08:00
Powered by Gitea Version: 1.27.1 Page: 36ms Template: 3ms
Dark
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API