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riscv
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rocket-chip
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Activity
36cba65e60
rocket-chip
/
vsim
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Andrew Waterman
e26363a176
Don't pass deprecated -ffaaf option to firrtl (
#1221
)
2018-02-01 14:46:38 -08:00
..
.gitignore
Write test harness in Chisel
2016-08-15 23:27:27 -07:00
Makefile
Use vlsi_mem_gen for verilator flow
2017-08-07 20:36:22 -07:00
Makefrag
Add in a SimJTAG to connect to OpenOCD's remote-bitbang interface.
2018-01-05 16:02:52 -08:00
Makefrag-verilog
Don't pass deprecated -ffaaf option to firrtl (
#1221
)
2018-02-01 14:46:38 -08:00