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Andrew Waterman ed827678ac Write test harness in Chisel 
This is an unavoidably invasive commit, because it affects the unit tests
(which formerly exited using stop()), the test harness Verilog generator
(since it is no longer necessary), and the DRAM model (since it is no
longer connected).  However, this should substantially reduce the effort
of building test harnesses in the future, since manual or semi-automatic
Verilog writing should no longer be necessary.  Furthermore, there is now
very little duplication of effort between the Verilator and VCS test
harnesses.

This commit removes support for DRAMsim, which is a bit of an unfortunate
consequence.  The main blocker is the lack of Verilog parameterization for
BlackBox.  It would be straightforward to revive DRAMsim once support for
that feature is added to Chisel and FIRRTL.  But that might not even be
necessary, as we move towards synthesizable DRAM models and FAME-1
transformations.
2016-08-15 23:27:27 -07:00
..
src/main/scala Write test harness in Chisel 2016-08-15 23:27:27 -07:00
.gitignore add .gitignore 2014-08-18 19:27:50 -07:00
build.sbt Add ability to generate libraryDependency on cde. 2015-10-22 11:37:20 -07:00
LICENSE add LICENSE 2014-09-12 15:36:42 -07:00
README.md update README 2014-09-17 11:23:25 -07:00

README.md

Rocket Core

Rocket is a 6-stage single-issue in-order pipeline that executes the 64-bit scalar RISC-V ISA. Rocket implements an MMU that supports page-based virtual memory and is able to boot modern operating systems such as Linux. Rocket also has an optional IEEE 754-2008-compliant FPU, which implements both single- and double-precision floating-point operations, including fused multiply-add.

This repository is not intended to be a self-running repository. To instantiate a Rocket core, please use the Rocket chip generator found in the rocket-chip git repository.

The following table compares a 32-bit ARM Cortex-A5 core to a 64-bit RISC-V Rocket core built in the same TSMC process (40GPLUS). Fourth column is the ratio of RISC-V Rocket to ARM Cortex-A5. Both use single-instruction-issue, in-order pipelines, yet the RISC-V core is faster, smaller, and uses less power.

ISA/Implementation ARM Cortex-A5 RISC-V Rocket R/A
ISA Register Width 32 bits 64 bits 2
Frequency >1 GHz >1 GHz 1
Dhrystone Performance 1.57 DMIPS/MHz 1.72 DMIPS/MHz 1.1
Area excluding caches 0.27 mm2 0.14 mm2 0.5
Area with 16KB caches 0.53 mm2 0.39 mm2 0.7
Area Efficiency 2.96 DMIPS/MHz/mm2 4.41 DMIPS/MHz/mm2 1.5
Dynamic Power <0.08 mW/MHz 0.034 mW/MHz >= 0.4