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The SCR file is gone, too, because it is tightly coupled. The general concept could be revived as a module that somehow connects to (or is contained by) the debug module. |
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| LICENSE | ||
| README.md | ||
Uncore Library
This is the repository for uncore components assosciated with Rocket chip project. To uses these modules, include this repo as a git submodule within the your chip repository and add it as a project in your chip's build.scala. These components are only dependent on the ucb-bar/chisel repo, i.e.
lazy val uncore = project.dependsOn(chisel)
ScalaDoc for the uncore library is available here and an overview of the TileLink Protocol is available here, with associated CoherencePolicy documentation here.