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rocket-chip
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Activity
35464782b5
rocket-chip
/
src
/
main
/
scala
History
Megan Wachs
35464782b5
PLIC: maxPriorities comes from params
2017-07-13 15:57:10 -07:00
..
amba
apb: SRAM can emulate incompletely populated memory
2017-07-07 21:40:40 -07:00
chip
Refactor package hierarchy and remove legacy bus protocol implementations (
#845
)
2017-07-07 10:48:16 -07:00
config
Refactor package hierarchy and remove legacy bus protocol implementations (
#845
)
2017-07-07 10:48:16 -07:00
coreplex
rocket: do not require FIFO order for memory-like regions
2017-07-12 17:39:00 -07:00
devices
PLIC: maxPriorities comes from params
2017-07-13 15:57:10 -07:00
diplomacy
diplomacy: add a new UNCACHEABLE RegionType
2017-07-12 16:31:50 -07:00
groundtest
Refactor package hierarchy and remove legacy bus protocol implementations (
#845
)
2017-07-07 10:48:16 -07:00
jtag
Use chisel3 Clock() method.
2017-07-07 14:16:39 -07:00
regmapper
regmapper: add byte-sized RegField helper function (
#854
)
2017-07-10 21:08:02 -07:00
rocket
rocket: do not require FIFO order for memory-like regions
2017-07-12 17:39:00 -07:00
tile
Refactor package hierarchy and remove legacy bus protocol implementations (
#845
)
2017-07-07 10:48:16 -07:00
tilelink
tilelink: FIFOFixer must support null cases (
#860
)
2017-07-12 22:20:31 -07:00
unittest
Refactor package hierarchy and remove legacy bus protocol implementations (
#845
)
2017-07-07 10:48:16 -07:00
util
Refactor package hierarchy and remove legacy bus protocol implementations (
#845
)
2017-07-07 10:48:16 -07:00