Andrew Waterman 33eaf08b60 set missing port direction ... Ideally, chisel should flag this as an error.		2016-08-29 12:31:52 -07:00
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coreplex	Streamline the Generator App and associated utilities. Remove deprecated call to chiselMain and useless Chisel2 args. Update arguments to sbt run. (#227)	2016-08-25 17:26:28 -07:00
groundtest	reorganize moving non-submodule packages into src/main/scala	2016-08-19 13:45:23 -07:00
junctions	JtagIO's DRV_TDO should be an INPUT	2016-08-19 16:38:03 -07:00
rocket	set missing port direction	2016-08-29 12:31:52 -07:00
rocketchip	Incorporate feedback to make the NExtPerhipheryInterrupts come from DeviceBlock itself	2016-08-26 10:40:39 -07:00
uncore	This commit adds Logic & test support for JTAG implementation of Debug Transport Module.	2016-08-19 16:08:31 -07:00