276 lines
8.2 KiB
Scala
276 lines
8.2 KiB
Scala
package junctions
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import Chisel._
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class SMIReq(val dataWidth: Int, val addrWidth: Int) extends Bundle {
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val rw = Bool()
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val addr = UInt(width = addrWidth)
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val data = Bits(width = dataWidth)
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override def cloneType =
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new SMIReq(dataWidth, addrWidth).asInstanceOf[this.type]
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}
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/** Simple Memory Interface IO. Used to communicate with PCR and SCR
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* @param dataWidth the width in bits of the data field
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* @param addrWidth the width in bits of the addr field */
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class SMIIO(val dataWidth: Int, val addrWidth: Int) extends Bundle {
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val req = Decoupled(new SMIReq(dataWidth, addrWidth))
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val resp = Decoupled(Bits(width = dataWidth)).flip
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override def cloneType =
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new SMIIO(dataWidth, addrWidth).asInstanceOf[this.type]
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}
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abstract class SMIPeripheral extends Module {
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val dataWidth: Int
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val addrWidth: Int
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lazy val io = new SMIIO(dataWidth, addrWidth).flip
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}
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/** A simple sequential memory accessed through SMI */
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class SMIMem(val dataWidth: Int, val memDepth: Int) extends SMIPeripheral {
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// override
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val addrWidth = log2Up(memDepth)
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val mem = SeqMem(Bits(width = dataWidth), memDepth)
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val ren = io.req.fire() && !io.req.bits.rw
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val wen = io.req.fire() && io.req.bits.rw
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when (wen) { mem.write(io.req.bits.addr, io.req.bits.data) }
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val resp_valid = Reg(init = Bool(false))
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when (io.resp.fire()) { resp_valid := Bool(false) }
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when (io.req.fire()) { resp_valid := Bool(true) }
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io.resp.valid := resp_valid
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io.resp.bits := mem.read(io.req.bits.addr, ren)
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io.req.ready := !resp_valid
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}
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/** Arbitrate among several SMI clients
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* @param n the number of clients
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* @param dataWidth SMI data width
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* @param addrWidth SMI address width */
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class SMIArbiter(val n: Int, val dataWidth: Int, val addrWidth: Int)
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extends Module {
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val io = new Bundle {
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val in = Vec(new SMIIO(dataWidth, addrWidth), n).flip
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val out = new SMIIO(dataWidth, addrWidth)
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}
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val wait_resp = Reg(init = Bool(false))
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val choice = Reg(UInt(width = log2Up(n)))
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val req_arb = Module(new RRArbiter(new SMIReq(dataWidth, addrWidth), n))
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req_arb.io.in <> io.in.map(_.req)
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req_arb.io.out.ready := io.out.req.ready && !wait_resp
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io.out.req.bits := req_arb.io.out.bits
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io.out.req.valid := req_arb.io.out.valid && !wait_resp
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when (io.out.req.fire()) {
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choice := req_arb.io.chosen
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wait_resp := Bool(true)
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}
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when (io.out.resp.fire()) { wait_resp := Bool(false) }
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for ((resp, i) <- io.in.map(_.resp).zipWithIndex) {
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resp.bits := io.out.resp.bits
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resp.valid := io.out.resp.valid && choice === UInt(i)
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}
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io.out.resp.ready := io.in(choice).resp.ready
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}
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class SMIIONASTIReadIOConverter(val dataWidth: Int, val addrWidth: Int)
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extends NASTIModule {
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val io = new Bundle {
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val ar = Decoupled(new NASTIReadAddressChannel).flip
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val r = Decoupled(new NASTIReadDataChannel)
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val smi = new SMIIO(dataWidth, addrWidth)
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}
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private val maxWordsPerBeat = nastiXDataBits / dataWidth
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private val wordCountBits = log2Up(maxWordsPerBeat)
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private val byteOffBits = log2Up(dataWidth / 8)
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private val addrOffBits = addrWidth + byteOffBits
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private def calcWordCount(size: UInt): UInt =
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(UInt(1) << (size - UInt(byteOffBits))) - UInt(1)
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val (s_idle :: s_read :: s_resp :: Nil) = Enum(Bits(), 3)
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val state = Reg(init = s_idle)
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val nWords = Reg(UInt(width = wordCountBits))
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val nBeats = Reg(UInt(width = nastiXLenBits))
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val addr = Reg(UInt(width = addrWidth))
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val id = Reg(UInt(width = nastiRIdBits))
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val byteOff = Reg(UInt(width = byteOffBits))
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val sendInd = Reg(init = UInt(0, wordCountBits))
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val recvInd = Reg(init = UInt(0, wordCountBits))
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val sendDone = Reg(init = Bool(false))
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val buffer = Reg(init = Vec(maxWordsPerBeat, Bits(0, dataWidth)))
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io.ar.ready := (state === s_idle)
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io.smi.req.valid := (state === s_read) && !sendDone
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io.smi.req.bits.rw := Bool(false)
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io.smi.req.bits.addr := addr
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io.smi.resp.ready := (state === s_read)
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io.r.valid := (state === s_resp)
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io.r.bits := NASTIReadDataChannel(
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id = id,
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data = buffer.toBits,
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last = (nBeats === UInt(0)))
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when (io.ar.fire()) {
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when (io.ar.bits.size < UInt(byteOffBits)) {
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nWords := UInt(0)
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byteOff := io.ar.bits.addr(byteOffBits - 1, 0)
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} .otherwise {
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nWords := calcWordCount(io.ar.bits.size)
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byteOff := UInt(0)
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}
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nBeats := io.ar.bits.len
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addr := io.ar.bits.addr(addrOffBits - 1, byteOffBits)
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id := io.ar.bits.id
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state := s_read
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}
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when (io.smi.req.fire()) {
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addr := addr + UInt(1)
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sendInd := sendInd + UInt(1)
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sendDone := (sendInd === nWords)
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}
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when (io.smi.resp.fire()) {
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recvInd := recvInd + UInt(1)
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buffer(recvInd) := io.smi.resp.bits >> Cat(byteOff, UInt(0, 3))
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when (recvInd === nWords) { state := s_resp }
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}
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when (io.r.fire()) {
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recvInd := UInt(0)
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sendInd := UInt(0)
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sendDone := Bool(false)
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// clear all the registers in the buffer
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buffer.foreach(_ := Bits(0))
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nBeats := nBeats - UInt(1)
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state := Mux(io.r.bits.last, s_idle, s_read)
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}
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}
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class SMIIONASTIWriteIOConverter(val dataWidth: Int, val addrWidth: Int)
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extends NASTIModule {
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val io = new Bundle {
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val aw = Decoupled(new NASTIWriteAddressChannel).flip
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val w = Decoupled(new NASTIWriteDataChannel).flip
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val b = Decoupled(new NASTIWriteResponseChannel)
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val smi = new SMIIO(dataWidth, addrWidth)
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}
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private val dataBytes = dataWidth / 8
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private val maxWordsPerBeat = nastiXDataBits / dataWidth
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private val byteOffBits = log2Floor(dataBytes)
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private val addrOffBits = addrWidth + byteOffBits
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assert(!io.aw.valid || io.aw.bits.size >= UInt(byteOffBits),
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"NASTI size must be >= SMI size")
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val id = Reg(UInt(width = nastiWIdBits))
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val addr = Reg(UInt(width = addrWidth))
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def makeStrobe(size: UInt, strb: UInt) = {
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val sizemask = (UInt(1) << (UInt(1) << size)) - UInt(1)
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val bytemask = sizemask & strb
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Vec.tabulate(maxWordsPerBeat){i => bytemask(dataBytes * i)}.toBits
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//val strbmask = Vec.tabulate(maxWordsPerBeat){i => strb(dataBytes * i)}.toBits
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//sizemask & strbmask
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}
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val size = Reg(UInt(width = nastiXSizeBits))
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val strb = Reg(UInt(width = maxWordsPerBeat))
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val data = Reg(UInt(width = nastiXDataBits))
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val last = Reg(Bool())
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val s_idle :: s_data :: s_send :: s_ack :: s_resp :: Nil = Enum(Bits(), 5)
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val state = Reg(init = s_idle)
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io.aw.ready := (state === s_idle)
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io.w.ready := (state === s_data)
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io.smi.req.valid := (state === s_send) && strb(0)
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io.smi.req.bits.rw := Bool(true)
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io.smi.req.bits.addr := addr
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io.smi.req.bits.data := data(dataWidth - 1, 0)
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io.smi.resp.ready := (state === s_ack)
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io.b.valid := (state === s_resp)
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io.b.bits := NASTIWriteResponseChannel(id)
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val jump = PriorityMux(strb(maxWordsPerBeat - 1, 1),
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(1 until maxWordsPerBeat).map(UInt(_)))
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when (io.aw.fire()) {
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addr := io.aw.bits.addr(addrOffBits - 1, byteOffBits)
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id := io.aw.bits.id
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//size := io.aw.bits.size - UInt(byteOffBits)
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size := io.aw.bits.size
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last := Bool(false)
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state := s_data
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}
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when (io.w.fire()) {
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last := io.w.bits.last
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strb := makeStrobe(size, io.w.bits.strb)
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data := io.w.bits.data
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state := s_send
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}
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when (state === s_send) {
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when (strb === UInt(0)) {
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state := Mux(last, s_ack, s_data)
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} .elsewhen (io.smi.req.ready || !strb(0)) {
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strb := strb >> jump
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data := data >> Cat(jump, UInt(0, log2Up(dataWidth)))
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addr := addr + jump
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}
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}
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when (io.smi.resp.fire()) { state := s_resp }
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when (io.b.fire()) { state := s_idle }
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}
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/** Convert NASTI protocol to SMI protocol */
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class SMIIONASTIIOConverter(val dataWidth: Int, val addrWidth: Int)
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extends NASTIModule {
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val io = new Bundle {
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val nasti = (new NASTIIO).flip
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val smi = new SMIIO(dataWidth, addrWidth)
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}
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require(isPow2(dataWidth), "SMI data width must be power of 2")
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val reader = Module(new SMIIONASTIReadIOConverter(dataWidth, addrWidth))
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reader.io.ar <> io.nasti.ar
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io.nasti.r <> reader.io.r
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val writer = Module(new SMIIONASTIWriteIOConverter(dataWidth, addrWidth))
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writer.io.aw <> io.nasti.aw
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writer.io.w <> io.nasti.w
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io.nasti.b <> writer.io.b
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val arb = Module(new SMIArbiter(2, dataWidth, addrWidth))
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arb.io.in(0) <> reader.io.smi
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arb.io.in(1) <> writer.io.smi
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io.smi <> arb.io.out
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}
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