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rocket-chip/rocket/src
Andrew Waterman 2b26082132 use 1r1w ram for tags; merge tags & permissions
setting the dirty bit now allocates an MSHR (to reuse the existing datapath)
2012-11-20 04:09:26 -08:00
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main/scala use 1r1w ram for tags; merge tags & permissions 2012-11-20 04:09:26 -08:00