Andrew Waterman 2aee85cb11 Flush pipeline from MEM stage ... This means we no longer have to rely on the instruction behind a serializing instruction being valid, simplifying the control. But we have to be a little more cautious when flusing the I$/ITLB/BTB.		2015-01-04 16:40:16 -08:00
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main/scala	Flush pipeline from MEM stage	2015-01-04 16:40:16 -08:00