Howard Mao cd96a66ba6 replace verilog clock divider with one written in Chisel		2016-09-22 11:32:29 -07:00
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.gitignore	Write test harness in Chisel	2016-08-15 23:27:27 -07:00
Makefile	Use PROJECT rather than MODEL in name of binary and generated src files.	2016-09-19 13:23:17 -07:00
Makefrag	replace verilog clock divider with one written in Chisel	2016-09-22 11:32:29 -07:00
Makefrag-verilog	[testharness] vsim makefrag cleanup	2016-09-19 15:14:45 -07:00
vlsi_mem_gen	fix null statement in vsli_mem_gen ala firrtl#264 (#252)	2016-09-07 11:04:36 -07:00