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riscv/rocket-chip
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1be13d6b4c2679e8890eca51447ace26380cd264
rocket-chip/src/main/scala/uncore
T
History
Megan Wachs 1be13d6b4c PLIC: To avoid hazard between enable -> claim, enforce concurrency=1
2017-04-19 21:37:37 -07:00
..
agents
Heterogeneous Tiles (#550)
2017-02-09 13:59:09 -08:00
ahb
AHBToTL: finally get the error signal right? (#594)
2017-03-18 22:24:20 -07:00
apb
apb: put both aFlow options under regression
2017-03-16 15:36:14 -07:00
axi4
axi4: use common BufferParams
2017-03-16 15:32:17 -07:00
coherence
copyright: ran scripts/modify-copyright
2016-11-27 22:15:43 -08:00
converters
Refactor Tile to use cake pattern (#502)
2017-01-16 18:24:08 -08:00
devices
PLIC: To avoid hazard between enable -> claim, enforce concurrency=1
2017-04-19 21:37:37 -07:00
tilelink
Refactor Tile to use cake pattern (#502)
2017-01-16 18:24:08 -08:00
tilelink2
Permit early grant acks to broadcast hub
2017-04-18 00:47:58 -07:00
util
Heterogeneous Tiles (#550)
2017-02-09 13:59:09 -08:00
Consts.scala
Check AMO operation legality in TLB
2017-04-14 01:03:11 -07:00
Package.scala
copyright: ran scripts/modify-copyright
2016-11-27 22:15:43 -08:00
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