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rocket-chip/src/main/scala
Andrew Waterman 1bac2cbdf8 Give Rocket priority over DTIM TL port
The TL port can easily starve the processor, even at only 20% utilization,
because of a bad interaction with the pipeline.  Giving the processor
static priority is OK in practice, since <50% of instructions are loads
and stores in typical workloads.  Even if it executes 100% loads and stores,
it must eventually encounter an I$ miss, taken branch, or exception, so
even malicious code can't permanently starve the TL port.
2018-02-20 11:23:10 -08:00
..
amba Error device: require explicit control of atomic and transfer sizes 2017-12-08 13:41:09 -08:00
config config: remove deprecated Parameters.root 2018-01-30 11:52:44 -08:00
coreplex Explicitly name PlusArg serializers as *_cHeader 2018-01-15 17:00:12 -05:00
devices Merge pull request #1239 from freechipsproject/reduce_debug_flags 2018-02-16 08:53:41 -08:00
diplomacy diplomacy: run user instantiate() method after nodes are initialized (#1198) 2018-01-18 14:57:47 -08:00
groundtest tile: BaseTileModule => BaseTileModuleImp 2018-01-02 17:55:54 -08:00
interrupts diplomacy: provide a val name for all LazyModule constructions 2017-12-01 11:28:21 -08:00
jtag JTAG: Use new withClock way of overriding clocks (#1072) 2018-01-17 13:59:05 -08:00
regmapper RegFieldDesc: don't put characters into names that need to be sanitized 2018-02-15 13:25:06 -08:00
rocket HellaCache: we do NOT really support probe below the block size! 2018-02-15 19:08:43 -08:00
system Add in a SimJTAG to connect to OpenOCD's remote-bitbang interface. 2018-01-05 16:02:52 -08:00
tile Give Rocket priority over DTIM TL port 2018-02-20 11:23:10 -08:00
tilelink RegFieldDesc: fix the output produced for undescribed registers 2018-02-16 10:24:12 -08:00
unittest Emit plusArgs for unit tests 2018-01-15 17:54:40 -05:00
util ElaborationArtefacts: revert unintentional change 2018-02-15 14:23:54 -08:00