74b6a8d02b
* [rocket] Refactor Tile into cake pattern with traits * [rocket] cacheDataBits &etc in HasCoreParameters * [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters * [rocket] frontend and icache now diplomatic * [rocket] file name capitalization * [rocket] re-add hook for inserting externally-defined Cores * [rocket] add FPUCoreIO * [groundtest] move TL1 Config instances to where they are used * [unittest] remove legacy unit tests * [groundtest] remove legacy device tests |
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| .. | ||
| Arbiters.scala | ||
| Crossing.scala | ||
| Definitions.scala | ||
| Drivers.scala | ||
| Interconnect.scala | ||
| Network.scala | ||