299 lines
6.8 KiB
Verilog
299 lines
6.8 KiB
Verilog
/*
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* TCP/IP controlled VPI JTAG Interface.
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* Based on Julius Baxter's work on jp_vpi.c
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*
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* Copyright (C) 2012 Franck Jullien, <franck.jullien@gmail.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the names of the copyright holders nor the names of any
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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`define CMD_RESET 0
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`define CMD_TMS_SEQ 1
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`define CMD_SCAN_CHAIN 2
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`define CMD_SCAN_CHAIN_FLIP_TMS 3
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`define CMD_STOP_SIMU 4
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module JTAGVPI
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#( parameter DEBUG_INFO = 0,
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parameter TP = 1,
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parameter TCK_HALF_PERIOD = 2,// 50, // Clock half period (Clock period = 100 ns => 10 MHz)
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parameter CMD_DELAY = 2 // 1000
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)
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(
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output jtag_TMS,
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output jtag_TCK,
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output jtag_TDI,
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input jtag_TDO,
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input jtag_TRST, // unused
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input enable,
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input init_done);
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reg tms;
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reg tck;
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reg tdi;
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wire tdo;
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assign jtag_TMS = tms;
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assign jtag_TCK = tck;
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assign jtag_TDI = tdi;
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assign tdo = jtag_TDO;
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integer cmd;
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integer length;
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integer nb_bits;
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reg [31:0] buffer_out [0:4095]; // Data storage from the jtag server
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reg [31:0] buffer_in [0:4095]; // Data storage to the jtag server
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integer flip_tms;
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reg [31:0] data_out;
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reg [31:0] data_in;
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integer debug;
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initial
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begin
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tck <= #TP 1'b0;
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tdi <= #TP 1'bz;
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tms <= #TP 1'b0;
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data_out <= 32'h0;
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data_in <= 32'h0;
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// Insert a #delay here because we need to
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// wait until the PC isn't pointing to flash anymore
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// (this is around 20k ns if the flash_crash boot code
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// is being booted from, else much bigger, around 10mil ns)
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wait(init_done)
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if($test$plusargs("jtag_vpi_enable")) main;
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end
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task main;
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begin
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$display("JTAG debug module with VPI interface enabled\n");
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reset_tap;
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goto_run_test_idle_from_reset;
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while (1) begin
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// Check for incoming command
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// wait until a command is sent
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// poll with a delay here
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cmd = -1;
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while (cmd == -1)
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begin
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#CMD_DELAY $check_for_command(cmd, length, nb_bits, buffer_out);
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end
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// now switch on the command
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case (cmd)
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`CMD_RESET :
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begin
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if (DEBUG_INFO)
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$display("%t ----> CMD_RESET %h\n", $time, length);
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reset_tap;
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goto_run_test_idle_from_reset;
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end
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`CMD_TMS_SEQ :
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begin
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if (DEBUG_INFO)
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$display("%t ----> CMD_TMS_SEQ\n", $time);
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do_tms_seq;
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end
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`CMD_SCAN_CHAIN :
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begin
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if (DEBUG_INFO)
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$display("%t ----> CMD_SCAN_CHAIN\n", $time);
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flip_tms = 0;
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do_scan_chain;
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$send_result_to_server(length, buffer_in);
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end
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`CMD_SCAN_CHAIN_FLIP_TMS :
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begin
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if(DEBUG_INFO)
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$display("%t ----> CMD_SCAN_CHAIN\n", $time);
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flip_tms = 1;
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do_scan_chain;
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$send_result_to_server(length, buffer_in);
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end
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`CMD_STOP_SIMU :
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begin
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if(DEBUG_INFO)
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$display("%t ----> End of simulation\n", $time);
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$finish();
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end
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default:
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begin
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$display("Somehow got to the default case in the command case statement.");
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$display("Command was: %x", cmd);
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$display("Exiting...");
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$finish();
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end
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endcase // case (cmd)
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end // while (1)
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end
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endtask // main
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// Generation of the TCK signal
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task gen_clk;
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input [31:0] number;
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integer i;
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begin
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for (i = 0; i < number; i = i + 1)
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begin
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#TCK_HALF_PERIOD tck <= 1;
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#TCK_HALF_PERIOD tck <= 0;
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end
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end
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endtask
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// TAP reset
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task reset_tap;
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begin
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if (DEBUG_INFO)
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$display("(%0t) Task reset_tap", $time);
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tms <= #1 1'b1;
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gen_clk(5);
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end
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endtask
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// Goes to RunTestIdle state
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task goto_run_test_idle_from_reset;
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begin
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if (DEBUG_INFO)
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$display("(%0t) Task goto_run_test_idle_from_reset", $time);
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tms <= #1 1'b0;
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gen_clk(1);
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end
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endtask
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//
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task do_tms_seq;
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integer i,j;
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reg [31:0] data;
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integer nb_bits_rem;
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integer nb_bits_in_this_byte;
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begin
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if (DEBUG_INFO)
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$display("(%0t) Task do_tms_seq of %d bits (length = %d)", $time, nb_bits, length);
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// Number of bits to send in the last byte
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nb_bits_rem = nb_bits % 8;
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for (i = 0; i < length; i = i + 1)
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begin
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// If we are in the last byte, we have to send only
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// nb_bits_rem bits. If not, we send the whole byte.
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nb_bits_in_this_byte = (i == (length - 1)) ? nb_bits_rem : 8;
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data = buffer_out[i];
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for (j = 0; j < nb_bits_in_this_byte; j = j + 1)
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begin
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tms <= #1 1'b0;
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if (data[j] == 1) begin
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tms <= #1 1'b1;
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end
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gen_clk(1);
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end
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end
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tms <= #1 1'b0;
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end
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endtask
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//
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task do_scan_chain;
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integer _bit;
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integer nb_bits_rem;
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integer nb_bits_in_this_byte;
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integer index;
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begin
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if(DEBUG_INFO)
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$display("(%0t) Task do_scan_chain of %d bits (length = %d)", $time, nb_bits, length);
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// Number of bits to send in the last byte
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nb_bits_rem = nb_bits % 8;
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for (index = 0; index < length; index = index + 1)
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begin
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// If we are in the last byte, we have to send only
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// nb_bits_rem bits if it's not zero.
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// If not, we send the whole byte.
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nb_bits_in_this_byte = (index == (length - 1)) ? ((nb_bits_rem == 0) ? 8 : nb_bits_rem) : 8;
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data_out = buffer_out[index];
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for (_bit = 0; _bit < nb_bits_in_this_byte; _bit = _bit + 1)
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begin
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tdi <= 1'b0;
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if (data_out[_bit] == 1'b1) begin
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tdi <= 1'b1;
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end
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// On the last bit, set TMS to '1'
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if (((_bit == (nb_bits_in_this_byte - 1)) && (index == (length - 1))) && (flip_tms == 1)) begin
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tms <= 1'b1;
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end
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#TCK_HALF_PERIOD tck <= 1;
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data_in[_bit] <= tdo;
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#TCK_HALF_PERIOD tck <= 0;
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end
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buffer_in[index] = data_in;
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end
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tdi <= 1'b0;
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tms <= 1'b0;
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end
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endtask
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endmodule
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