4c595d175c
* Refactors package hierarchy. Additionally: - Removes legacy ground tests and configs - Removes legacy bus protocol implementations - Removes NTiles - Adds devices package - Adds more functions to util package
30 lines
921 B
Scala
30 lines
921 B
Scala
// See LICENSE.jtag for license details.
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package freechips.rocketchip.jtag
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import chisel3._
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import chisel3.util._
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class JTAGIdcodeBundle extends Bundle {
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val version = UInt(4.W)
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val partNumber = UInt(16.W)
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val mfrId = UInt(11.W)
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val always1 = UInt(1.W)
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}
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object JtagIdcode {
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/** Generates a JTAG IDCODE as a 32-bit integer, using the format in 12.1.1d.
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*/
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def apply(version: Int, partNumber: Int, mfrId: Int): BigInt = {
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require(version < (1 << 4), "version field must be 4 bits at most")
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require(partNumber < (1 << 16), "part number must be 16 bits at most")
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require(mfrId < (1 << 11), "manufacturer identity must be 11 bits at most")
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BigInt(version) << 28 | BigInt(partNumber) << 12 | BigInt(mfrId) << 1 | 1
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}
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/** A dummy manufacturer ID, not to be used per 12.2.1b since bus masters may shift this out to
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* determine the end of a bus.
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*/
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def dummyMfrId: Int = 0x7f
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}
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