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rocket-chip/uncore
Henry Cook 16bfbda3c9 Refactor the TransactionTracker logic in all the L2 TileLink Managers.
They now share common sub-transactions within traits, and use a common
set of state transitions and scoreboarding logic. Tracker allocation
logic has also been updated. No changes to external IOs or the TileLink protocol.
A new bufferless Broadcast hub is also included, but does not yet pass fuzzing checks.
2016-06-16 15:18:48 -07:00
..
project add plugins to make scala doc site and publish to ghpages 2015-04-29 15:34:56 -07:00
src/main/scala Refactor the TransactionTracker logic in all the L2 TileLink Managers. 2016-06-16 15:18:48 -07:00
.gitignore First pages commit 2015-04-29 13:18:26 -07:00
build.sbt Add ability to generate libraryDependency on cde. 2015-10-22 09:57:02 -07:00
LICENSE First pages commit 2015-04-29 13:18:26 -07:00
README.md update README.md 2015-07-29 11:49:21 -07:00

Uncore Library

This is the repository for uncore components assosciated with Rocket chip project. To uses these modules, include this repo as a git submodule within the your chip repository and add it as a project in your chip's build.scala. These components are only dependent on the ucb-bar/chisel repo, i.e.

lazy val uncore = project.dependsOn(chisel)

ScalaDoc for the uncore library is available here and an overview of the TileLink Protocol is available here, with associated CoherencePolicy documentation here.