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riscv/rocket-chip
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1285fa909fcf55cf1ff70ba902696e78105326a9
rocket-chip/src/main/scala
T
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Henry CookandGitHub 0fe2899c74 [tracegen] remove TL1 noisemaker, use io.finish and catch simulation exit (#528)
2017-01-25 12:10:49 -08:00
..
config
Configs: use a uniform syntax without Match exceptions (#507)
2017-01-13 14:41:19 -08:00
coreplex
coreplex: provide coherence managers with geometry information
2017-01-23 15:50:39 -08:00
diplomacy
diplomacy: find names of LazyModules also in Seq() member values (#527)
2017-01-24 18:10:37 -08:00
groundtest
[tracegen] remove TL1 noisemaker, use io.finish and catch simulation exit (#528)
2017-01-25 12:10:49 -08:00
junctions
Refactor Tile to use cake pattern (#502)
2017-01-16 18:24:08 -08:00
regmapper
copyright: ran scripts/modify-copyright
2016-11-27 22:15:43 -08:00
rocket
rocket: L1 only needs cache-line transfer sizes
2017-01-19 19:07:14 -08:00
rocketchip
coreplex: support multiple memory channels via diplomatic trickery
2017-01-19 19:07:14 -08:00
uncore
tilelink2: disable A=>D bypass in ToAXI4 whenever possible
2017-01-24 18:11:00 -08:00
unittest
Refactor Tile to use cake pattern (#502)
2017-01-16 18:24:08 -08:00
util
diplomacy: make config.Parameters available in bundle connect()
2016-12-07 12:24:01 -08:00
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