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riscv/rocket-chip
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0edcd3304a2b7b2f6ed281a7947cfd094ec0fcd6
rocket-chip/src/main/scala/rocketchip
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Wesley W. Terpstra ec2d23b8b7 rocketchip: Bundle-slices need access to the outer LazyModule
We need this change in order for some ports to use parameters that result
from LazyModule diplomacy.

Now you can eat your cake too!
2016-10-31 11:41:18 -07:00
..
BaseTop.scala
rocketchip: Bundle-slices need access to the outer LazyModule
2016-10-31 11:41:18 -07:00
Configs.scala
rocketchip: include an socBus between l1tol2 and periphery (#415)
2016-10-24 23:56:09 -07:00
DebugTransport.scala
debug: use a different form of the crossing which doesn't create an AsyncScope (#394)
2016-10-09 20:33:18 -07:00
ExampleTop.scala
rocketchip: Bundle-slices need access to the outer LazyModule
2016-10-31 11:41:18 -07:00
Generator.scala
rocketchip: generate GraphML output
2016-09-26 14:35:46 -07:00
Periphery.scala
diplomacy: guess the LazyModule name from the containing class
2016-10-25 15:58:09 -07:00
RocketTestSuite.scala
fix typo rv64iu -> rv64ui
2016-09-22 17:33:35 -07:00
TestHarness.scala
don't use Scala to Chisel implicit conversions outside of rocket
2016-09-29 14:35:42 -07:00
Utils.scala
rocketchip: remove obsolete pDevices used during TL1=>2 migration
2016-10-31 11:41:18 -07:00
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