Wesley W. TerpstraandAndrew Waterman 0ab5cb67b3 tilelink: fix RAMModel handling of AMOs on early source reuse (#897)

2017-07-27 11:07:13 -07:00

..

amba

Combine Coreplex and System Module Hierarchies (#875)

2017-07-23 08:31:04 -07:00

config

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

coreplex

coreplex: better names for RocketTiles in Verilog (#890)

2017-07-25 16:35:31 -07:00

devices

tilelink: remove obsolete addr_lo signal (#895)

2017-07-26 16:01:21 -07:00

diplomacy

Combine Coreplex and System Module Hierarchies (#875)

2017-07-23 08:31:04 -07:00

groundtest

chiplink: adjust bus view to include the splitter (#886)

2017-07-24 21:41:17 -07:00

jtag

Use chisel3 Clock() method.

2017-07-07 14:16:39 -07:00

regmapper

add cloneType to RegisterWriteIO and RegisterReadIO (#874)

2017-07-18 18:52:31 -07:00

rocket

tilelink: remove obsolete addr_lo signal (#895)

2017-07-26 16:01:21 -07:00

system

Mix in trait to connect global_reset_vector

2017-07-25 15:19:16 -07:00

tile

Perform some control-flow transfers within the Frontend

2017-07-25 15:19:16 -07:00

tilelink

tilelink: fix RAMModel handling of AMOs on early source reuse (#897)

2017-07-27 11:07:13 -07:00

unittest

Combine Coreplex and System Module Hierarchies (#875)

2017-07-23 08:31:04 -07:00

util

Combine Coreplex and System Module Hierarchies (#875)

2017-07-23 08:31:04 -07:00