ea9f0a868f
We have a handful of TileLink-related helper objects (wrappers, unwrappers, width adapters, and enqueuers). Previously, using them could be error-prone, because you had to make sure the implicit parameters they took in had the same TLId as the TileLinkIO bundles passed in as inputs. This is rather silly, we should just use the parameters in the bundle.
85 lines
3.0 KiB
Scala
85 lines
3.0 KiB
Scala
package coreplex
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import Chisel._
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import cde.{Parameters, Field}
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import junctions._
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import uncore.tilelink._
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import uncore.util._
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import rocket._
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trait DirectConnection {
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val tiles: Seq[Tile]
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val uncoreTileIOs: Seq[TileIO]
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val tlBuffering = TileLinkDepths(1,1,2,2,0)
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val ultBuffering = UncachedTileLinkDepths(1,2)
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(tiles zip uncoreTileIOs) foreach { case (tile, uncore) =>
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(uncore.cached zip tile.io.cached) foreach { case (u, t) => u <> TileLinkEnqueuer(t, tlBuffering) }
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(uncore.uncached zip tile.io.uncached) foreach { case (u, t) => u <> TileLinkEnqueuer(t, ultBuffering) }
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tile.io.slave.foreach { _ <> TileLinkEnqueuer(uncore.slave.get, 1) }
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tile.io.interrupts <> uncore.interrupts
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tile.io.hartid := uncore.hartid
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tile.io.resetVector := uncore.resetVector
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}
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}
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class DefaultCoreplex(c: CoreplexConfig)(implicit p: Parameters) extends BaseCoreplex(c)(p) {
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override lazy val module = Module(new DefaultCoreplexModule(c, this, new DefaultCoreplexBundle(c)(p))(p))
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}
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class DefaultCoreplexBundle(c: CoreplexConfig)(implicit p: Parameters) extends BaseCoreplexBundle(c)(p)
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class DefaultCoreplexModule[+L <: DefaultCoreplex, +B <: DefaultCoreplexBundle](
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c: CoreplexConfig, l: L, b: => B)(implicit p: Parameters) extends BaseCoreplexModule(c, l, b)(p)
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with DirectConnection
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/////
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trait TileClockResetBundle {
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val c: CoreplexConfig
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val tcrs = Vec(c.nTiles, new Bundle {
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val clock = Clock(INPUT)
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val reset = Bool(INPUT)
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})
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}
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trait AsyncConnection {
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val io: TileClockResetBundle
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val tiles: Seq[Tile]
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val uncoreTileIOs: Seq[TileIO]
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(tiles, uncoreTileIOs, io.tcrs).zipped foreach { case (tile, uncore, tcr) =>
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tile.clock := tcr.clock
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tile.reset := tcr.reset
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(uncore.cached zip tile.io.cached) foreach { case (u, t) => u <> AsyncTileLinkFrom(tcr.clock, tcr.reset, t) }
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(uncore.uncached zip tile.io.uncached) foreach { case (u, t) => u <> AsyncUTileLinkFrom(tcr.clock, tcr.reset, t) }
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tile.io.slave.foreach { _ <> AsyncUTileLinkTo(tcr.clock, tcr.reset, uncore.slave.get)}
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val ti = tile.io.interrupts
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val ui = uncore.interrupts
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ti.debug := LevelSyncTo(tcr.clock, ui.debug)
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ti.mtip := LevelSyncTo(tcr.clock, ui.mtip)
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ti.msip := LevelSyncTo(tcr.clock, ui.msip)
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ti.meip := LevelSyncTo(tcr.clock, ui.meip)
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ti.seip.foreach { _ := LevelSyncTo(tcr.clock, ui.seip.get) }
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tile.io.hartid := uncore.hartid
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tile.io.resetVector := uncore.resetVector
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}
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}
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class MultiClockCoreplex(c: CoreplexConfig)(implicit p: Parameters) extends BaseCoreplex(c)(p) {
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override lazy val module = Module(new MultiClockCoreplexModule(c, this, new MultiClockCoreplexBundle(c)(p))(p))
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}
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class MultiClockCoreplexBundle(c: CoreplexConfig)(implicit p: Parameters) extends BaseCoreplexBundle(c)(p)
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with TileClockResetBundle
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class MultiClockCoreplexModule[+L <: MultiClockCoreplex, +B <: MultiClockCoreplexBundle](
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c: CoreplexConfig, l: L, b: => B)(implicit p: Parameters) extends BaseCoreplexModule(c, l, b)(p)
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with AsyncConnection
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