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rocket-chip/fsim/Makefile
2014-09-08 00:21:57 -07:00

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Makefile

#=======================================================================
# Makefile for Verilog simulation w/ VCS
#-----------------------------------------------------------------------
# Yunsup Lee (yunsup@cs.berkeley.edu)
#
# This makefile will build a rtl simulator and run various tests to
# verify proper functionality.
#
default: all
base_dir = $(abspath ..)
generated_dir = $(abspath ./generated-src)
mem_gen = $(base_dir)/fsim/fpga_mem_gen
sim_dir = .
output_dir = $(sim_dir)/output
BACKEND = fpga
CONFIG = DefaultFPGAConfig
include $(base_dir)/Makefrag
include $(sim_dir)/Makefrag
include $(base_dir)/vsim/Makefrag-sim
all: $(simv)
clean:
rm -rf $(junk) simv* csrc *.key DVE* *.h *.a *.daidir $(generated_dir)