Wesley W. Terpstra 05e7501e7a build: include chiselName and give an example of using it (#738)

2017-05-12 06:25:58 -07:00

..

Arbiter.scala

axi4: switch arbiter to round robin

2017-05-01 22:53:41 -07:00

AsyncCrossing.scala

tilelink2: annotate which test generates RAMModel output

2017-04-14 15:13:40 -07:00

AtomicAutomata.scala

tilelink2: annotate which test generates RAMModel output

2017-04-14 15:13:40 -07:00

Atomics.scala

tilelink2: add a generic TL2 atomic evaulation unit

2017-04-14 15:13:39 -07:00

Broadcast.scala

Permit early grant acks to broadcast hub

2017-04-18 00:47:58 -07:00

Buffer.scala

TLBuffer: move TLBufferParams to diplomacy.BufferParams

2017-03-16 15:19:36 -07:00

Bundles.scala

rocketchip: work-around ucb-bar/chisel3#472

2017-01-31 14:20:02 -08:00

CacheCork.scala

CacheCork: remove probe support

2017-04-11 12:34:18 -07:00

Delayer.scala

TLDelayer: insert noise on invalid cycles

2017-03-11 02:53:43 -08:00

Edges.scala

tilelink2: define is{Request,Response} based on spec

2017-03-20 13:41:02 -07:00

Error.scala

tilelink2: Error device for returning errors on demand

2017-05-01 22:53:02 -07:00

Example.scala

uncore: add DTS meta-data for devices

2017-03-02 21:19:22 -08:00

FIFOFixer.scala

tilelink2: FIFOFixer should NOT change client request status

2017-05-01 22:53:41 -07:00

Filter.scala

uncore: switch to new diplomacy Node API

2017-01-29 15:54:45 -08:00

Fragmenter.scala

tilelink2: add earlyAck to regression

2017-05-09 17:35:26 -07:00

Fuzzer.scala

diplomacy: add legalize method to AddressSet

2017-05-10 12:54:24 -07:00

HintHandler.scala

tilelink2: annotate which test generates RAMModel output

2017-04-14 15:13:40 -07:00

IntNodes.scala

graphML: reverse interrupt arrows

2017-04-14 18:09:14 -07:00

Isolation.scala

tilelink2: split suportsAcquire into T and B variants

2017-01-19 19:07:13 -08:00

Legacy.scala

diplomacy: make config.Parameters available in bundle connect()

2016-12-07 12:24:01 -08:00

Metadata.scala

rocketchip: work-around ucb-bar/chisel3#472

2017-01-31 14:20:02 -08:00

Monitor.scala

tilelink2 Monitor: catch incorrect use of source ID

2017-03-27 16:30:46 -07:00

Nodes.scala

diplomacy: use HeterogeneousBag instead of Vec

2017-02-22 17:05:22 -08:00

package.scala

tilelink2: better width inference for {left,right}OR

2017-05-01 22:53:41 -07:00

Parameters.scala

diplomacy: optimize IdRange overlap detection

2017-05-01 22:53:41 -07:00

RAMModel.scala

tilelink2: RAMModel, use CRC16 to check AMO response

2017-04-14 15:13:40 -07:00

RationalCrossing.scala

tilelink2: annotate which test generates RAMModel output

2017-04-14 15:13:40 -07:00

RegisterRouter.scala

RegisterRouter: support devices with gaps

2017-03-20 14:49:22 -07:00

RegisterRouterTest.scala

Tests: include more random delays

2017-03-11 02:53:43 -08:00

Repeater.scala

copyright: ran scripts/modify-copyright

2016-11-27 22:15:43 -08:00

SourceShrinker.scala

tilelink2 SourceShrinker: destroy FIFO behaviour

2017-03-21 11:16:51 -07:00

SRAM.scala

build: include chiselName and give an example of using it (#738)

2017-05-12 06:25:58 -07:00

TestRAM.scala

tilelink2: annotate which test generates RAMModel output

2017-04-14 15:13:40 -07:00

ToAHB.scala

ToAHB: appease AHB VIP

2017-03-16 15:17:05 -07:00

ToAPB.scala

TLToAPB: use the now standard aFlow parameter name

2017-03-16 15:34:59 -07:00

ToAXI4.scala

tilelink: ToAXI4 - must interlock till last beat

2017-05-08 00:17:06 -07:00

WidthWidget.scala

tilelink2: help tools save some registers in the WidthWidget (#691)

2017-04-24 15:13:58 -07:00

Xbar.scala

tilelink2: annotate which test generates RAMModel output

2017-04-14 15:13:40 -07:00

Zero.scala

uncore: add DTS meta-data for devices

2017-03-02 21:19:22 -08:00