| .. |
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Arbiter.scala
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axi4: switch arbiter to round robin
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2017-05-01 22:53:41 -07:00 |
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AsyncCrossing.scala
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tilelink2: annotate which test generates RAMModel output
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2017-04-14 15:13:40 -07:00 |
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AtomicAutomata.scala
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tilelink2: annotate which test generates RAMModel output
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2017-04-14 15:13:40 -07:00 |
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Atomics.scala
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tilelink2: add a generic TL2 atomic evaulation unit
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2017-04-14 15:13:39 -07:00 |
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Broadcast.scala
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Permit early grant acks to broadcast hub
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2017-04-18 00:47:58 -07:00 |
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Buffer.scala
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TLBuffer: move TLBufferParams to diplomacy.BufferParams
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2017-03-16 15:19:36 -07:00 |
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Bundles.scala
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rocketchip: work-around ucb-bar/chisel3#472
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2017-01-31 14:20:02 -08:00 |
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CacheCork.scala
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CacheCork: remove probe support
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2017-04-11 12:34:18 -07:00 |
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Delayer.scala
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TLDelayer: insert noise on invalid cycles
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2017-03-11 02:53:43 -08:00 |
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Edges.scala
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tilelink2: define is{Request,Response} based on spec
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2017-03-20 13:41:02 -07:00 |
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Error.scala
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tilelink2: Error device for returning errors on demand
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2017-05-01 22:53:02 -07:00 |
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Example.scala
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uncore: add DTS meta-data for devices
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2017-03-02 21:19:22 -08:00 |
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FIFOFixer.scala
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tilelink2: FIFOFixer should NOT change client request status
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2017-05-01 22:53:41 -07:00 |
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Filter.scala
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uncore: switch to new diplomacy Node API
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2017-01-29 15:54:45 -08:00 |
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Fragmenter.scala
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tilelink2: add earlyAck to regression
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2017-05-09 17:35:26 -07:00 |
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Fuzzer.scala
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diplomacy: add legalize method to AddressSet
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2017-05-10 12:54:24 -07:00 |
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HintHandler.scala
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tilelink2: annotate which test generates RAMModel output
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2017-04-14 15:13:40 -07:00 |
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IntNodes.scala
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graphML: reverse interrupt arrows
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2017-04-14 18:09:14 -07:00 |
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Isolation.scala
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tilelink2: split suportsAcquire into T and B variants
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2017-01-19 19:07:13 -08:00 |
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Legacy.scala
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diplomacy: make config.Parameters available in bundle connect()
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2016-12-07 12:24:01 -08:00 |
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Metadata.scala
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rocketchip: work-around ucb-bar/chisel3#472
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2017-01-31 14:20:02 -08:00 |
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Monitor.scala
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tilelink2 Monitor: catch incorrect use of source ID
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2017-03-27 16:30:46 -07:00 |
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Nodes.scala
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diplomacy: use HeterogeneousBag instead of Vec
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2017-02-22 17:05:22 -08:00 |
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package.scala
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tilelink2: better width inference for {left,right}OR
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2017-05-01 22:53:41 -07:00 |
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Parameters.scala
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diplomacy: optimize IdRange overlap detection
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2017-05-01 22:53:41 -07:00 |
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RAMModel.scala
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tilelink2: RAMModel, use CRC16 to check AMO response
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2017-04-14 15:13:40 -07:00 |
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RationalCrossing.scala
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tilelink2: annotate which test generates RAMModel output
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2017-04-14 15:13:40 -07:00 |
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RegisterRouter.scala
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RegisterRouter: support devices with gaps
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2017-03-20 14:49:22 -07:00 |
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RegisterRouterTest.scala
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Tests: include more random delays
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2017-03-11 02:53:43 -08:00 |
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Repeater.scala
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copyright: ran scripts/modify-copyright
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2016-11-27 22:15:43 -08:00 |
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SourceShrinker.scala
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tilelink2 SourceShrinker: destroy FIFO behaviour
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2017-03-21 11:16:51 -07:00 |
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SRAM.scala
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build: include chiselName and give an example of using it (#738)
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2017-05-12 06:25:58 -07:00 |
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TestRAM.scala
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tilelink2: annotate which test generates RAMModel output
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2017-04-14 15:13:40 -07:00 |
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ToAHB.scala
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ToAHB: appease AHB VIP
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2017-03-16 15:17:05 -07:00 |
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ToAPB.scala
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TLToAPB: use the now standard aFlow parameter name
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2017-03-16 15:34:59 -07:00 |
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ToAXI4.scala
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tilelink: ToAXI4 - must interlock till last beat
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2017-05-08 00:17:06 -07:00 |
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WidthWidget.scala
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tilelink2: help tools save some registers in the WidthWidget (#691)
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2017-04-24 15:13:58 -07:00 |
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Xbar.scala
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tilelink2: annotate which test generates RAMModel output
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2017-04-14 15:13:40 -07:00 |
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Zero.scala
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uncore: add DTS meta-data for devices
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2017-03-02 21:19:22 -08:00 |
