33 lines
887 B
Scala
33 lines
887 B
Scala
package rocket
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import Chisel._
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import Node._;
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class rocketCtrlSboard(entries: Int, nread: Int, nwrite: Int) extends Component
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{
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class read_port extends Bundle {
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val addr = UFix(log2Up(entries), INPUT)
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val data = Bool(OUTPUT)
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}
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class write_port extends Bundle {
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val en = Bool(INPUT)
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val addr = UFix(log2Up(entries), INPUT)
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val data = Bool(INPUT)
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}
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val io = new Bundle {
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val r = Vec(nread) { new read_port() }
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val w = Vec(nwrite) { new write_port() }
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}
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val busybits = Reg(resetVal = Bits(0, entries))
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val wmasks = (0 until nwrite).map(i => Fill(entries, io.w(i).en) & (UFix(1) << io.w(i).addr))
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val wdatas = (0 until nwrite).map(i => Mux(io.w(i).data, wmasks(i), UFix(0)))
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var next = busybits & ~wmasks.reduceLeft(_|_) | wdatas.reduceLeft(_|_)
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busybits := next
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for (i <- 0 until nread)
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io.r(i).data := busybits(io.r(i).addr)
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}
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