147 lines
5.1 KiB
Scala
147 lines
5.1 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.util
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import Chisel._
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// Similar to the Chisel ShiftRegister but allows the user to suggest a
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// name to the registers that get instantiated, and
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// to provide a reset value.
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object ShiftRegInit {
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def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
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(0 until n).foldRight(in) {
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case (i, next) => {
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val r = Reg(next, next = next, init = init)
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name.foreach { na => r.suggestName(s"${na}_${i}") }
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r
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}
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}
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}
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/** These wrap behavioral
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* shift registers into specific modules to allow for
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* backend flows to replace or constrain
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* them properly when used for CDC synchronization,
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* rather than buffering.
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*
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* The different types vary in their reset behavior:
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* AsyncResetShiftReg -- This is identical to the AsyncResetSynchronizerShiftReg,
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* it is just named differently to distinguish its use case.
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* This is an async ShiftRegister meant for timing,
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* not for synchronization.
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* AsyncResetSynchronizerShiftReg -- asynchronously reset to specific value.
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* SyncResetSynchronizerShiftReg -- reset to specific value.
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* SynchronizerShiftReg -- no reset, pipeline only.
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*/
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abstract class AbstractPipelineReg(w: Int = 1) extends Module {
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val io = new Bundle {
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val d = UInt(INPUT, width = w)
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val q = UInt(OUTPUT, width = w)
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}
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}
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object AbstractPipelineReg {
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def apply [T <: Chisel.Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
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val chain = Module(gen)
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name.foreach{ chain.suggestName(_) }
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chain.io.d := in.asUInt
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chain.io.q.asTypeOf(in)
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}
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}
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class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
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require(depth > 0, "Depth must be greater than 0.")
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override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
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val chain = List.tabulate(depth) { i =>
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Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
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}
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chain.last.io.d := io.d
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chain.last.io.en := Bool(true)
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(chain.init zip chain.tail).foreach { case (sink, source) =>
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sink.io.d := source.io.q
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sink.io.en := Bool(true)
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}
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io.q := chain.head.io.q
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}
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object AsyncResetShiftReg {
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def apply [T <: Chisel.Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
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AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
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def apply [T <: Chisel.Data](in: T, depth: Int, name: Option[String]): T =
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apply(in, depth, 0, name)
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def apply [T <: Chisel.Data](in: T, depth: Int, init: T, name: Option[String]): T =
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apply(in, depth, init.litValue.toInt, name)
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def apply [T <: Chisel.Data](in: T, depth: Int, init: T): T =
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apply (in, depth, init.litValue.toInt, None)
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}
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// Note that it is important to ovveride "name" in order to ensure that the Chisel dedup does
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// not try to merge instances of this with instances of the superclass.
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class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int = 3, init: Int = 0) extends AsyncResetShiftReg(w, depth = sync, init, name = "sync") {
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require(sync > 0, "Sync must be greater than 0.")
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override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
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}
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object AsyncResetSynchronizerShiftReg {
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def apply [T <: Chisel.Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
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AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, depth, init), in, name)
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def apply [T <: Chisel.Data](in: T, depth: Int, name: Option[String]): T =
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apply(in, depth, 0, name)
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def apply [T <: Chisel.Data](in: T, depth: Int, init: T, name: Option[String]): T =
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apply(in, depth, init.litValue.toInt, name)
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def apply [T <: Chisel.Data](in: T, depth: Int, init: T): T =
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apply (in, depth, init.litValue.toInt, None)
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}
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class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
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require(sync > 0, "Sync must be greater than 0.")
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override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
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val syncv = List.tabulate(sync) { i =>
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val r = Reg(UInt(width = w))
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r.suggestName(s"sync_${i}")
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}
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syncv.last := io.d
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(syncv.init zip syncv.tail).foreach { case (sink, source) =>
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sink := source
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}
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io.q := syncv.head
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}
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object SynchronizerShiftReg {
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def apply [T <: Chisel.Data](in: T, sync: Int = 3, name: Option[String] = None): T = {
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if (sync == 0) in
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else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
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}
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}
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class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int = 3, init: Int = 0) extends AbstractPipelineReg(w) {
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require (sync >= 0, "Sync must be greater than or equal to 0")
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override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
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io.q := ShiftRegInit(io.d, n = sync, init = init.U, name = Some("sync"))
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}
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object SyncResetSynchronizerShiftReg {
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def apply [T <: Chisel.Data](in: T, sync: Int = 3, init: T, name: Option[String] = None): T =
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AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init.litValue.toInt), in, name)
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}
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