86 lines
2.2 KiB
Scala
86 lines
2.2 KiB
Scala
// See LICENSE.Berkeley for license details.
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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.util
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import Chisel._
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abstract class ReplacementPolicy {
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def way: UInt
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def miss: Unit
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def hit: Unit
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}
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class RandomReplacement(ways: Int) extends ReplacementPolicy {
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private val replace = Wire(Bool())
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replace := Bool(false)
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val lfsr = LFSR16(replace)
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def way = if(ways == 1) UInt(0) else lfsr(log2Up(ways)-1,0)
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def miss = replace := Bool(true)
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def hit = {}
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}
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abstract class SeqReplacementPolicy {
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def access(set: UInt): Unit
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def update(valid: Bool, hit: Bool, set: UInt, way: UInt): Unit
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def way: UInt
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}
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class SeqRandom(n_ways: Int) extends SeqReplacementPolicy {
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val logic = new RandomReplacement(n_ways)
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def access(set: UInt) = { }
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def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = {
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when (valid && !hit) { logic.miss }
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}
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def way = logic.way
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}
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class PseudoLRU(n: Int)
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{
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private val state_reg = Reg(UInt(width = n-1))
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def access(way: UInt) {
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state_reg := get_next_state(state_reg,way)
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}
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def get_next_state(state: UInt, way: UInt) = {
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var next_state = state << 1
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var idx = UInt(1,1)
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for (i <- log2Up(n)-1 to 0 by -1) {
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val bit = way(i)
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next_state = next_state.bitSet(idx, !bit)
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idx = Cat(idx, bit)
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}
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next_state(n-1, 1)
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}
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def replace = get_replace_way(state_reg)
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def get_replace_way(state: UInt) = {
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val shifted_state = state << 1
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var idx = UInt(1,1)
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for (i <- log2Up(n)-1 to 0 by -1) {
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val in_bounds = Cat(idx, UInt(BigInt(1) << i))(log2Up(n)-1, 0) < UInt(n)
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idx = Cat(idx, in_bounds && shifted_state(idx))
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}
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idx(log2Up(n)-1,0)
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}
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}
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class SeqPLRU(n_sets: Int, n_ways: Int) extends SeqReplacementPolicy {
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val state = SeqMem(n_sets, UInt(width = n_ways-1))
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val logic = new PseudoLRU(n_ways)
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val current_state = Wire(UInt())
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val plru_way = logic.get_replace_way(current_state)
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val next_state = Wire(UInt())
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def access(set: UInt) = {
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current_state := state.read(set)
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}
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def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = {
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val update_way = Mux(hit, way, plru_way)
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next_state := logic.get_next_state(current_state, update_way)
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when (valid) { state.write(set, next_state) }
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}
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def way = plru_way
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}
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