40 lines
1.1 KiB
Scala
40 lines
1.1 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.util
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import Chisel._
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// A Repeater passes it's input to it's output, unless repeat is asserted.
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// When repeat is asserted, the Repeater copies the input and repeats it next cycle.
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class Repeater[T <: Data](gen: T) extends Module
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{
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val io = new Bundle {
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val repeat = Bool(INPUT)
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val full = Bool(OUTPUT)
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val enq = Decoupled(gen).flip
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val deq = Decoupled(gen)
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}
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val full = RegInit(Bool(false))
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val saved = Reg(gen)
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// When !full, a repeater is pass-through
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io.deq.valid := io.enq.valid || full
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io.enq.ready := io.deq.ready && !full
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io.deq.bits := Mux(full, saved, io.enq.bits)
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io.full := full
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when (io.enq.fire() && io.repeat) { full := Bool(true); saved := io.enq.bits }
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when (io.deq.fire() && !io.repeat) { full := Bool(false) }
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}
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object Repeater
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{
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def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = {
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val repeater = Module(new Repeater(enq.bits))
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repeater.io.repeat := repeat
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repeater.io.enq := enq
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repeater.io.deq
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}
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}
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