100 lines
3.3 KiB
Scala
100 lines
3.3 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.util
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import Chisel._
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case class PositionalMultiQueueParameters[T <: Data](gen: T, positions: Int, ways: Int)
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class PositionalMultiQueueEntry[T <: Data](params: PositionalMultiQueueParameters[T])
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extends GenericParameterizedBundle(params)
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{
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val data = params.gen.asOutput
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val pos = UInt(width = log2Up(params.positions))
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}
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class PositionalMultiQueuePush[T <: Data](params: PositionalMultiQueueParameters[T])
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extends PositionalMultiQueueEntry(params)
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{
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val way = UInt(width = log2Up(params.ways))
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}
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/* A PositionalMultiQueue is like a normal Queue, except that it stores (position, value).
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* When you pop it, you get back the oldest (position, value) pushed into it.
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* >>>>> You must guarantee that you never enque to an occupied position. <<<<<
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* Unlike a normal Queue, a PositionalMultiQueue has multiple deque ports (ways).
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* You select which way will deque a given (position, value) when you enque it.
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* If combinational, deque ports become valid on the same cycle as the enque.
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*/
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class PositionalMultiQueue[T <: Data](params: PositionalMultiQueueParameters[T], combinational: Boolean) extends Module
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{
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val io = new Bundle {
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val enq = Valid(new PositionalMultiQueuePush(params)).flip
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val deq = Vec(params.ways, Decoupled(new PositionalMultiQueueEntry(params)))
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}
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val empty = RegInit(Vec.fill(params.ways) { Bool(true) })
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val head = Reg(Vec(params.ways, UInt(width = log2Up(params.positions))))
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val tail = Reg(Vec(params.ways, UInt(width = log2Up(params.positions))))
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val next = Mem(params.positions, UInt(width = log2Up(params.positions)))
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val data = Mem(params.positions, params.gen)
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// optimized away for synthesis; used to confirm invariant
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val guard = RegInit(UInt(0, width = params.positions))
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when (io.enq.fire()) {
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data(io.enq.bits.pos) := io.enq.bits.data
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// ensure the user never stores to the same position twice
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assert (!guard(io.enq.bits.pos))
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when (!empty(io.enq.bits.way)) {
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next(tail(io.enq.bits.way)) := io.enq.bits.pos
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}
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}
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val setGuard = io.enq.fire() << io.enq.bits.pos
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val deq = Wire(io.deq)
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io.deq <> deq
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val waySelect = UIntToOH(io.enq.bits.way, params.ways)
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var clrGuard = UInt(0)
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for (i <- 0 until params.ways) {
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val enq = io.enq.fire() && waySelect(i)
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val last = head(i) === tail(i)
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when (enq) {
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tail(i) := io.enq.bits.pos
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when (empty(i)) {
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head(i) := io.enq.bits.pos
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}
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}
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if (combinational) {
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deq(i).valid := !empty(i) || enq
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deq(i).bits.pos := Mux(empty(i), io.enq.bits.pos, head(i))
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deq(i).bits.data := Mux(empty(i), io.enq.bits.data, data(head(i)))
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} else {
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deq(i).valid := !empty(i)
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deq(i).bits.pos := head(i)
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deq(i).bits.data := data(head(i))
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}
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when (deq(i).fire()) {
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head(i) := Mux(last, io.enq.bits.pos, next(head(i)))
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}
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clrGuard = clrGuard | (deq(i).fire() << deq(i).bits.pos)
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when (enq =/= deq(i).fire()) {
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empty(i) := deq(i).fire() && last
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}
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}
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guard := (guard | setGuard) & ~clrGuard
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}
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object PositionalMultiQueue
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{
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def apply[T <: Data](gen: T, positions: Int, ways: Int = 1, combinational: Boolean = true) = {
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Module(new PositionalMultiQueue(PositionalMultiQueueParameters(gen, positions, ways), combinational))
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}
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}
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