56 lines
1.4 KiB
Scala
56 lines
1.4 KiB
Scala
// See LICENSE.SiFive for license details.
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// See LICENSE.Berkeley for license details.
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package freechips.rocketchip.util
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import Chisel._
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/** A 16-bit psuedo-random generator based on a linear conguential
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* generator (LCG). The state is stored in an unitialised register.
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* When using the C++ backend, it is straigtforward to arrange a
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* random initial value for each uninitialised register, effectively
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* seeding each LCG16 instance with a different seed.
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*/
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class LCG16 extends Module {
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val io = new Bundle {
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val out = UInt(OUTPUT, 16)
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val inc = Bool(INPUT)
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}
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val state = Reg(UInt(width = 32))
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when (io.inc) {
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state := state * UInt(1103515245, 32) + UInt(12345, 32)
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}
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io.out := state(30, 15)
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}
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/** An n-bit psuedo-random generator made from many instances of a
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* 16-bit LCG. Parameter 'width' must be larger than 0.
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*/
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class LCG(val w: Int) extends Module {
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val io = new Bundle {
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val out = UInt(OUTPUT, w)
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val inc = Bool(INPUT)
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}
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require(w > 0)
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val numLCG16s : Int = (w+15)/16
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val outs = Seq.fill(numLCG16s) { LCG16(io.inc) }
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io.out := Cat(outs)
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}
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object LCG16 {
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def apply(inc: Bool = Bool(true)): UInt = {
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val lcg = Module(new LCG16)
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lcg.io.inc := inc
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lcg.io.out
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}
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}
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object LCG {
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def apply(w: Int, inc: Bool = Bool(true)): UInt = {
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val lcg = Module(new LCG(w))
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lcg.io.inc := inc
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lcg.io.out
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}
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}
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