70 lines
1.9 KiB
Scala
70 lines
1.9 KiB
Scala
// See LICENSE.Berkeley for license details.
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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.util
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import Chisel._
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import scala.math.max
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// Produces 0-width value when counting to 1
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class ZCounter(val n: Int) {
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val value = Reg(init=UInt(0, log2Ceil(n)))
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def inc(): Bool = {
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if (n == 1) Bool(true)
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else {
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val wrap = value === UInt(n-1)
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value := Mux(Bool(!isPow2(n)) && wrap, UInt(0), value + UInt(1))
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wrap
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}
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}
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}
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object ZCounter {
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def apply(n: Int) = new ZCounter(n)
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def apply(cond: Bool, n: Int): (UInt, Bool) = {
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val c = new ZCounter(n)
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var wrap: Bool = null
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when (cond) { wrap = c.inc() }
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(c.value, cond && wrap)
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}
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}
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object TwoWayCounter {
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def apply(up: Bool, down: Bool, max: Int): UInt = {
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val cnt = Reg(init = UInt(0, log2Up(max+1)))
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when (up && !down) { cnt := cnt + UInt(1) }
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when (down && !up) { cnt := cnt - UInt(1) }
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cnt
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}
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}
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// a counter that clock gates most of its MSBs using the LSB carry-out
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case class WideCounter(width: Int, inc: UInt = UInt(1), reset: Boolean = true)
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{
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private val isWide = width > 2*inc.getWidth
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private val smallWidth = if (isWide) inc.getWidth max log2Up(width) else width
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private val small = if (reset) Reg(init=UInt(0, smallWidth)) else Reg(UInt(width = smallWidth))
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private val nextSmall = small +& inc
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small := nextSmall
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private val large = if (isWide) {
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val r = if (reset) Reg(init=UInt(0, width - smallWidth)) else Reg(UInt(width = width - smallWidth))
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when (nextSmall(smallWidth)) { r := r + UInt(1) }
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r
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} else null
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val value = if (isWide) Cat(large, small) else small
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lazy val carryOut = {
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val lo = (small ^ nextSmall) >> 1
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if (!isWide) lo else {
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val hi = Mux(nextSmall(smallWidth), large ^ (large +& UInt(1)), UInt(0)) >> 1
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Cat(hi, lo)
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}
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}
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def := (x: UInt) = {
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small := x
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if (isWide) large := x >> smallWidth
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}
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}
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