110 lines
3.3 KiB
Scala
110 lines
3.3 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.util
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import Chisel._
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/** This black-boxes an Async Reset
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* (or Set)
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* Register.
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*
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* Because Chisel doesn't support
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* parameterized black boxes,
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* we unfortunately have to
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* instantiate a number of these.
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*
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* We also have to hard-code the set/
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* reset behavior.
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*
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* Do not confuse an asynchronous
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* reset signal with an asynchronously
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* reset reg. You should still
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* properly synchronize your reset
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* deassertion.
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*
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* @param d Data input
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* @param q Data Output
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* @param clk Clock Input
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* @param rst Reset Input
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* @param en Write Enable Input
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*
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*/
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class AsyncResetReg extends BlackBox {
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val io = new Bundle {
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val d = Bool(INPUT)
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val q = Bool(OUTPUT)
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val en = Bool(INPUT)
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val clk = Clock(INPUT)
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val rst = Bool(INPUT)
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}
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}
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class SimpleRegIO(val w: Int) extends Bundle{
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val d = UInt(INPUT, width = w)
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val q = UInt(OUTPUT, width = w)
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val en = Bool(INPUT)
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}
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class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module {
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val io = new SimpleRegIO(w)
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val async_regs = List.fill(w)(Module(new AsyncResetReg))
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val q = for ((reg, idx) <- async_regs.zipWithIndex) yield {
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def maybeInvert(x: Bool) = if (((init >> idx) & 1) == 1) !x else x
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reg.io.clk := clock
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reg.io.rst := reset
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reg.io.d := maybeInvert(io.d(idx))
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reg.io.en := io.en
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reg.suggestName(s"reg_$idx")
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maybeInvert(reg.io.q)
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}
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io.q := q.asUInt
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override def desiredName = s"AsyncResetRegVec_w${w}_i${init}"
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}
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object AsyncResetReg {
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// Create Single Registers
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def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = {
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def maybeInvert(x: Bool) = if (init) !x else x
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val reg = Module(new AsyncResetReg)
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reg.io.d := maybeInvert(d)
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reg.io.clk := clk
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reg.io.rst := rst
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reg.io.en := Bool(true)
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name.foreach(reg.suggestName(_))
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maybeInvert(reg.io.q)
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}
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def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None)
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def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name))
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// Create Vectors of Registers
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def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = {
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val w = updateData.getWidth max resetData.bitLength
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val reg = Module(new AsyncResetRegVec(w, resetData))
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name.foreach(reg.suggestName(_))
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reg.io.d := updateData
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reg.io.en := enable
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reg.io.q
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}
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def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData,
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resetData, enable, Some(name))
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def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable=Bool(true))
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def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable=Bool(true), Some(name))
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def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable)
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def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData=BigInt(0), enable, Some(name))
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def apply(updateData: UInt): UInt = apply(updateData, resetData=BigInt(0), enable=Bool(true))
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def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData=BigInt(0), enable=Bool(true), Some(name))
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}
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