176 lines
7.4 KiB
Scala
176 lines
7.4 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.util
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import Chisel._
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object GrayCounter {
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def apply(bits: Int, increment: Bool = Bool(true), clear: Bool = Bool(false), name: String = "binary"): UInt = {
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val incremented = Wire(UInt(width=bits))
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val binary = AsyncResetReg(incremented, name)
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incremented := Mux(clear, UInt(0), binary + increment.asUInt())
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incremented ^ (incremented >> UInt(1))
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}
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}
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class AsyncValidSync(sync: Int, desc: String) extends Module {
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val io = new Bundle {
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val in = Bool(INPUT)
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val out = Bool(OUTPUT)
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}
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io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
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}
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class AsyncQueueSource[T <: Data](gen: T, depth: Int, sync: Int, safe: Boolean = true, narrowData: Boolean = false) extends Module {
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val bits = log2Ceil(depth)
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val io = new Bundle {
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// These come from the source domain
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val enq = Decoupled(gen).flip
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// These cross to the sink clock domain
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val ridx = UInt(INPUT, width = bits+1)
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val widx = UInt(OUTPUT, width = bits+1)
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val mem = Vec(if(narrowData) 1 else depth, gen).asOutput
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val index = narrowData.option(UInt(INPUT, width = bits))
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// Signals used to self-stabilize a safe AsyncQueue
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val sink_reset_n = Bool(INPUT)
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val ridx_valid = Bool(INPUT)
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val widx_valid = Bool(OUTPUT)
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}
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val sink_ready = Wire(init = Bool(true))
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val mem = Reg(Vec(depth, gen)) // This does NOT need to be reset at all.
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val widx = GrayCounter(bits+1, io.enq.fire(), !sink_ready, "widx_bin")
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val ridx = AsyncResetSynchronizerShiftReg(io.ridx, sync, Some("ridx_gray"))
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val ready = sink_ready && widx =/= (ridx ^ UInt(depth | depth >> 1))
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val index = if (depth == 1) UInt(0) else io.widx(bits-1, 0) ^ (io.widx(bits, bits) << (bits-1))
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when (io.enq.fire()) { mem(index) := io.enq.bits }
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val ready_reg = AsyncResetReg(ready.asUInt, "ready_reg")(0)
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io.enq.ready := ready_reg && sink_ready
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val widx_reg = AsyncResetReg(widx, "widx_gray")
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io.widx := widx_reg
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if(narrowData) io.mem(0) := mem(io.index.get) else io.mem := mem
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io.widx_valid := Bool(true)
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if (safe) {
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val source_valid = Module(new AsyncValidSync(sync+1, "source_valid"))
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val sink_extend = Module(new AsyncValidSync(1, "sink_extend"))
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val sink_valid = Module(new AsyncValidSync(sync, "sink_valid"))
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source_valid.reset := reset || !io.sink_reset_n
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sink_extend .reset := reset || !io.sink_reset_n
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source_valid.io.in := Bool(true)
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io.widx_valid := source_valid.io.out
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sink_extend.io.in := io.ridx_valid
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sink_valid.io.in := sink_extend.io.out
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sink_ready := sink_valid.io.out
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// Assert that if there is stuff in the queue, then reset cannot happen
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// Impossible to write because dequeue can occur on the receiving side,
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// then reset allowed to happen, but write side cannot know that dequeue
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// occurred.
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// TODO: write some sort of sanity check assertion for users
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// that denote don't reset when there is activity
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// assert (!(reset || !io.sink_reset_n) || !io.enq.valid, "Enque while sink is reset and AsyncQueueSource is unprotected")
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// assert (!reset_rise || prev_idx_match.toBool, "Sink reset while AsyncQueueSource not empty")
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}
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}
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class AsyncQueueSink[T <: Data](gen: T, depth: Int, sync: Int, safe: Boolean = true, narrowData: Boolean = false) extends Module {
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val bits = log2Ceil(depth)
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val io = new Bundle {
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// These come from the sink domain
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val deq = Decoupled(gen)
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// These cross to the source clock domain
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val ridx = UInt(OUTPUT, width = bits+1)
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val widx = UInt(INPUT, width = bits+1)
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val mem = Vec(if(narrowData) 1 else depth, gen).asInput
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val index = narrowData.option(UInt(OUTPUT, width = bits))
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// Signals used to self-stabilize a safe AsyncQueue
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val source_reset_n = Bool(INPUT)
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val ridx_valid = Bool(OUTPUT)
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val widx_valid = Bool(INPUT)
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}
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val source_ready = Wire(init = Bool(true))
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val ridx = GrayCounter(bits+1, io.deq.fire(), !source_ready, "ridx_bin")
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val widx = AsyncResetSynchronizerShiftReg(io.widx, sync, Some("widx_gray"))
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val valid = source_ready && ridx =/= widx
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// The mux is safe because timing analysis ensures ridx has reached the register
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// On an ASIC, changes to the unread location cannot affect the selected value
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// On an FPGA, only one input changes at a time => mem updates don't cause glitches
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// The register only latches when the selected valued is not being written
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val index = if (depth == 1) UInt(0) else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
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if(narrowData) io.index.get := index
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// This register does not NEED to be reset, as its contents will not
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// be considered unless the asynchronously reset deq valid register is set.
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// It is possible that bits latches when the source domain is reset / has power cut
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// This is safe, because isolation gates brought mem low before the zeroed widx reached us
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val deq_bits_nxt = Mux(valid, io.mem(if(narrowData) UInt(0) else index), io.deq.bits)
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io.deq.bits := SynchronizerShiftReg(deq_bits_nxt, sync = 1, name = Some("deq_bits_reg"))
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val valid_reg = AsyncResetReg(valid.asUInt, "valid_reg")(0)
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io.deq.valid := valid_reg && source_ready
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val ridx_reg = AsyncResetReg(ridx, "ridx_gray")
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io.ridx := ridx_reg
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io.ridx_valid := Bool(true)
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if (safe) {
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val sink_valid = Module(new AsyncValidSync(sync+1, "sink_valid"))
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val source_extend = Module(new AsyncValidSync(1, "source_extend"))
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val source_valid = Module(new AsyncValidSync(sync, "source_valid"))
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sink_valid .reset := reset || !io.source_reset_n
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source_extend.reset := reset || !io.source_reset_n
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sink_valid.io.in := Bool(true)
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io.ridx_valid := sink_valid.io.out
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source_extend.io.in := io.widx_valid
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source_valid.io.in := source_extend.io.out
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source_ready := source_valid.io.out
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val reset_and_extend = !source_ready || !io.source_reset_n || reset
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val reset_and_extend_prev = Reg(Bool(), reset_and_extend, Bool(true))
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val reset_rise = !reset_and_extend_prev && reset_and_extend
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val prev_idx_match = AsyncResetReg(updateData=(io.widx===io.ridx), resetData=0)
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// TODO: write some sort of sanity check assertion for users
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// that denote don't reset when there is activity
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// assert (!reset_rise || prev_idx_match.toBool, "Source reset while AsyncQueueSink not empty")
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}
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}
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// If narrowData is true then the read mux is moved to the source side of the crossing.
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// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
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// at the expense of a combinational path from the sink to the source and back to the sink.
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class AsyncQueue[T <: Data](gen: T, depth: Int = 8, sync: Int = 3, safe: Boolean = true, narrowData: Boolean = false) extends Crossing[T] {
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require (sync >= 2)
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require (depth > 0 && isPow2(depth))
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val io = new CrossingIO(gen)
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val source = Module(new AsyncQueueSource(gen, depth, sync, safe, narrowData))
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val sink = Module(new AsyncQueueSink (gen, depth, sync, safe, narrowData))
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source.clock := io.enq_clock
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source.reset := io.enq_reset
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sink.clock := io.deq_clock
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sink.reset := io.deq_reset
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source.io.sink_reset_n := !io.deq_reset
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sink.io.source_reset_n := !io.enq_reset
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source.io.enq <> io.enq
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io.deq <> sink.io.deq
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sink.io.mem := source.io.mem
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if(narrowData) source.io.index.get <> sink.io.index.get
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sink.io.widx := source.io.widx
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source.io.ridx := sink.io.ridx
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sink.io.widx_valid := source.io.widx_valid
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source.io.ridx_valid := sink.io.ridx_valid
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}
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