94 lines
3.4 KiB
Scala
94 lines
3.4 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.tilelink
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import Chisel._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.amba.apb._
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import scala.math.{min, max}
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import APBParameters._
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case class TLToAPBNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, APBImp)(
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dFn = { case TLClientPortParameters(clients, minLatency) =>
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val masters = clients.map { case c => APBMasterParameters(name = c.name, nodePath = c.nodePath) }
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APBMasterPortParameters(masters)
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},
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uFn = { case APBSlavePortParameters(slaves, beatBytes) =>
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val managers = slaves.map { case s =>
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TLManagerParameters(
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address = s.address,
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resources = s.resources,
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regionType = s.regionType,
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executable = s.executable,
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nodePath = s.nodePath,
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supportsGet = if (s.supportsRead) TransferSizes(1, beatBytes) else TransferSizes.none,
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supportsPutPartial = if (s.supportsWrite) TransferSizes(1, beatBytes) else TransferSizes.none,
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supportsPutFull = if (s.supportsWrite) TransferSizes(1, beatBytes) else TransferSizes.none,
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fifoId = Some(0)) // a common FIFO domain
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}
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TLManagerPortParameters(managers, beatBytes, 1, 0)
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})
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// The input side has either a flow queue (aFlow=true) or a pipe queue (aFlow=false)
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// The output side always has a flow queue
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class TLToAPB(val aFlow: Boolean = true)(implicit p: Parameters) extends LazyModule
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{
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val node = TLToAPBNode()
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lazy val module = new LazyModuleImp(this) {
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(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
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val beatBytes = edgeOut.slave.beatBytes
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val lgBytes = log2Ceil(beatBytes)
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// APB has no cache coherence
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in.b.valid := Bool(false)
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in.c.ready := Bool(true)
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in.e.ready := Bool(true)
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// We need a skidpad to capture D output:
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// We cannot know if the D response will be accepted until we have
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// presented it on D as valid. We also can't back-pressure APB in the
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// data phase. Therefore, we must have enough space to save the data
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// phase result. Whenever we have a queued response, we can not allow
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// APB to present new responses, so we must quash the address phase.
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val d = Wire(in.d)
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in.d <> Queue(d, 1, flow = true)
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// We need an irrevocable input for APB to stall
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val a = Queue(in.a, 1, flow = aFlow, pipe = !aFlow)
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val a_enable = RegInit(Bool(false))
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val a_sel = a.valid && RegNext(!in.d.valid || in.d.ready)
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val a_write = edgeIn.hasData(a.bits)
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when (a_sel) { a_enable := Bool(true) }
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when (d.fire()) { a_enable := Bool(false) }
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out.psel := a_sel
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out.penable := a_enable
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out.pwrite := a_write
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out.paddr := a.bits.address
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out.pprot := PROT_DEFAULT
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out.pwdata := a.bits.data
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out.pstrb := Mux(a_write, a.bits.mask, UInt(0))
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a.ready := a_enable && out.pready
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d.valid := a_enable && out.pready
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assert (!d.valid || d.ready)
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d.bits := edgeIn.AccessAck(a.bits, out.prdata, out.pslverr)
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d.bits.opcode := Mux(a_write, TLMessages.AccessAck, TLMessages.AccessAckData)
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}
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}
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}
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object TLToAPB
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{
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def apply(aFlow: Boolean = true)(implicit p: Parameters) =
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{
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val tl2apb = LazyModule(new TLToAPB(aFlow))
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tl2apb.node
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}
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}
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