195 lines
7.4 KiB
Scala
195 lines
7.4 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.tilelink
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import Chisel._
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import freechips.rocketchip.amba.ahb._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.util._
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import scala.math.{min, max}
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import AHBParameters._
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case class TLToAHBNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, AHBImp)(
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dFn = { case TLClientPortParameters(clients, minLatency) =>
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val masters = clients.map { case c => AHBMasterParameters(name = c.name, nodePath = c.nodePath) }
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AHBMasterPortParameters(masters)
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},
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uFn = { case AHBSlavePortParameters(slaves, beatBytes) =>
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val managers = slaves.map { case s =>
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TLManagerParameters(
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address = s.address,
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resources = s.resources,
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regionType = s.regionType,
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executable = s.executable,
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nodePath = s.nodePath,
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supportsGet = s.supportsRead,
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supportsPutFull = s.supportsWrite, // but not PutPartial
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fifoId = Some(0))
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}
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TLManagerPortParameters(managers, beatBytes, 1, 1)
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})
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class AHBControlBundle(params: TLEdge) extends GenericParameterizedBundle(params)
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{
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val full = Bool()
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val send = Bool() // => full+data
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val first = Bool()
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val last = Bool()
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val write = Bool()
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val size = UInt(width = params.bundle.sizeBits)
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val source = UInt(width = params.bundle.sourceBits)
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val hsize = UInt(width = AHBParameters.sizeBits)
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val hburst = UInt(width = AHBParameters.burstBits)
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val addr = UInt(width = params.bundle.addressBits)
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val data = UInt(width = params.bundle.dataBits)
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}
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// The input side has either a flow queue (aFlow=true) or a pipe queue (aFlow=false)
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// The output side always has a flow queue
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class TLToAHB(val aFlow: Boolean = false)(implicit p: Parameters) extends LazyModule
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{
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val node = TLToAHBNode()
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lazy val module = new LazyModuleImp(this) {
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(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
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val beatBytes = edgeOut.slave.beatBytes
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val maxTransfer = edgeOut.slave.maxTransfer
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val lgMax = log2Ceil(maxTransfer)
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val lgBytes = log2Ceil(beatBytes)
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// Initial FSM state
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val resetState = Wire(new AHBControlBundle(edgeIn))
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resetState.full := Bool(false)
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resetState.send := Bool(false)
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resetState.first := Bool(true)
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// These are needed to appease AHB VIP:
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resetState.hsize := UInt(0)
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resetState.hburst:= UInt(0)
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resetState.addr := UInt(0)
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// The stages of the combinational pipeline
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val reg = RegInit(resetState)
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val send = Wire(init = reg)
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val step = Wire(init = send)
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val next = Wire(init = step)
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reg := next
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// Advance the FSM based on the result of this AHB beat
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when (send.send && !out.hreadyout) /* retry AHB */ {
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step.full := Bool(true)
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step.send := Bool(true)
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} .elsewhen (send.full && !send.send) /* retry beat */ {
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step.full := Bool(true)
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step.send := Bool(false)
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} .elsewhen (send.full && !send.last) /* continue burst */ {
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step.full := Bool(true)
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step.send := Bool(false) // => looks like a retry to injector
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step.first := Bool(false)
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step.last := (if (lgBytes + 1 >= lgMax) Bool(true) else
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!((UIntToOH1(send.size, lgMax) & ~send.addr) >> (lgBytes + 1)).orR())
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step.addr := Cat(send.addr(edgeIn.bundle.addressBits-1, lgMax), send.addr(lgMax-1, 0) + UInt(beatBytes))
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} .otherwise /* new burst */ {
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step.full := Bool(false)
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step.send := Bool(false)
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step.first := Bool(true)
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}
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val d_block = Wire(Bool())
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val pre = if (aFlow) reg else step
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val post = if (aFlow) send else next
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// Transform TL size into AHB hsize+hburst
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val a_sizeDelta = Cat(UInt(0, width = 1), in.a.bits.size) - UInt(lgBytes+1)
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val a_singleBeat = Bool(lgBytes >= lgMax) || a_sizeDelta(edgeIn.bundle.sizeBits)
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val a_logBeats1 = a_sizeDelta(edgeIn.bundle.sizeBits-1, 0)
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// Pulse this every time we commit to sending an AHB request
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val a_commit = Wire(Bool())
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// Inject A channel into FSM
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when (pre.send) /* busy */ {
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a_commit := Bool(false)
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in.a.ready := Bool(false)
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} .elsewhen (pre.full) /* retry beat (or continue burst) */ {
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post.send := !d_block && (!pre.write || in.a.valid)
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post.data := in.a.bits.data
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a_commit := !d_block && !pre.write // only read beats commit to a D beat answer
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in.a.ready := !d_block && pre.write
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} .otherwise /* new burst */ {
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a_commit := in.a.fire() // every first beat commits to a D beat answer
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in.a.ready := !d_block
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when (in.a.fire()) {
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post.full := Bool(true)
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post.send := Bool(true)
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post.last := a_singleBeat
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post.write := edgeIn.hasData(in.a.bits)
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post.size := in.a.bits.size
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post.source:= in.a.bits.source
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post.hsize := Mux(a_singleBeat, in.a.bits.size, UInt(lgBytes))
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post.hburst:= Mux(a_singleBeat, BURST_SINGLE, (a_logBeats1<<1) | UInt(1))
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post.addr := in.a.bits.address
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post.data := in.a.bits.data
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}
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}
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out.hmastlock := Bool(false) // for now
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out.htrans := Mux(send.send, Mux(send.first, TRANS_NONSEQ, TRANS_SEQ), Mux(send.first, TRANS_IDLE, TRANS_BUSY))
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out.hsel := send.send || !send.first
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out.hready := out.hreadyout
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out.hwrite := send.write
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out.haddr := send.addr
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out.hsize := send.hsize
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out.hburst := send.hburst
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out.hprot := PROT_DEFAULT
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out.hwdata := RegEnable(send.data, out.hreadyout)
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// We need a skidpad to capture D output:
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// We cannot know if the D response will be accepted until we have
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// presented it on D as valid. We also can't back-pressure AHB in the
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// data phase. Therefore, we must have enough space to save the all
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// commited AHB requests (A+D phases = 2). To decouple d_ready from
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// a_ready and htrans, we add another entry for aFlow=false.
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val depth = if (aFlow) 2 else 3
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val d = Wire(in.d)
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in.d <> Queue(d, depth, flow=true)
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assert (!d.valid || d.ready)
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val d_flight = RegInit(UInt(0, width = 2))
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assert (d_flight <= UInt(depth))
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d_flight := d_flight + a_commit.asUInt - in.d.fire().asUInt
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d_block := d_flight >= UInt(depth)
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val d_valid = RegInit(Bool(false))
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val d_error = Reg(Bool())
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val d_write = RegEnable(send.write, out.hreadyout)
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val d_source = RegEnable(send.source, out.hreadyout)
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val d_size = RegEnable(send.size, out.hreadyout)
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when (out.hreadyout) {
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d_valid := send.send && (send.last || !send.write)
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when (out.hresp) { d_error := Bool(true) }
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when (send.first) { d_error := Bool(false) }
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}
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d.valid := d_valid && out.hreadyout
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d.bits := edgeIn.AccessAck(d_source, d_size, out.hrdata, out.hresp || d_error)
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d.bits.opcode := Mux(d_write, TLMessages.AccessAck, TLMessages.AccessAckData)
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// AHB has no cache coherence
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in.b.valid := Bool(false)
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in.c.ready := Bool(true)
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in.e.ready := Bool(true)
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}
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}
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}
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object TLToAHB
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{
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def apply(aFlow: Boolean = true)(implicit p: Parameters) =
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{
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val tl2ahb = LazyModule(new TLToAHB(aFlow))
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tl2ahb.node
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}
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}
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