83 lines
2.8 KiB
Scala
83 lines
2.8 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.tilelink
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import Chisel._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.util._
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import scala.math.{min,max}
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class TLSourceShrinker(maxInFlight: Int)(implicit p: Parameters) extends LazyModule
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{
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require (maxInFlight > 0)
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// The SourceShrinker completely destroys all FIFO property guarantees
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private val client = TLClientParameters(
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name = "TLSourceShrinker",
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sourceId = IdRange(0, maxInFlight))
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val node = TLAdapterNode(
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// We erase all client information since we crush the source Ids
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clientFn = { cp => TLClientPortParameters(clients = Seq(client.copy(requestFifo = cp.clients.exists(_.requestFifo)))) },
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managerFn = { mp => mp.copy(managers = mp.managers.map(m => m.copy(fifoId = if (maxInFlight==1) Some(0) else m.fifoId))) })
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lazy val module = new LazyModuleImp(this) {
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(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
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// Acquires cannot pass this adapter; it makes Probes impossible
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require (!edgeIn.client.anySupportProbe ||
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!edgeOut.manager.anySupportAcquireB)
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out.b.ready := Bool(true)
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out.c.valid := Bool(false)
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out.e.valid := Bool(false)
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in.b.valid := Bool(false)
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in.c.ready := Bool(true)
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in.e.ready := Bool(true)
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if (maxInFlight >= edgeIn.client.endSourceId) {
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out.a <> in.a
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in.d <> out.d
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} else {
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// State tracking
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val sourceIdMap = Mem(maxInFlight, in.a.bits.source)
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val allocated = RegInit(UInt(0, width = maxInFlight))
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val nextFreeOH = ~(leftOR(~allocated) << 1) & ~allocated
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val nextFree = OHToUInt(nextFreeOH)
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val full = allocated.andR()
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val a_first = edgeIn.first(in.a)
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val d_last = edgeIn.last(in.d)
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val block = a_first && full
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in.a.ready := out.a.ready && !block
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out.a.valid := in.a.valid && !block
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out.a.bits := in.a.bits
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out.a.bits.source := nextFree holdUnless a_first
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val bypass = Bool(edgeOut.manager.minLatency == 0) && in.a.fire() && a_first && nextFree === out.d.bits.source
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in.d <> out.d
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in.d.bits.source := Mux(bypass, in.a.bits.source, sourceIdMap(out.d.bits.source))
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when (a_first && in.a.fire()) {
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sourceIdMap(nextFree) := in.a.bits.source
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}
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val alloc = a_first && in.a.fire()
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val free = d_last && in.d.fire()
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val alloc_id = Mux(alloc, nextFreeOH, UInt(0))
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val free_id = Mux(free, UIntToOH(out.d.bits.source), UInt(0))
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allocated := (allocated | alloc_id) & ~free_id
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}
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}
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}
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}
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object TLSourceShrinker
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{
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def apply(maxInFlight: Int)(implicit p: Parameters): TLNode =
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{
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val shrinker = LazyModule(new TLSourceShrinker(maxInFlight))
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shrinker.node
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}
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}
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