118 lines
6.6 KiB
Scala
118 lines
6.6 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.tilelink
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import Chisel._
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import chisel3.internal.sourceinfo.SourceInfo
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.util.RationalDirection
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import scala.collection.mutable.ListBuffer
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case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
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object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
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{
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def edgeO(pd: TLClientPortParameters, pu: TLManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
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def edgeI(pd: TLClientPortParameters, pu: TLManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
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def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
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def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
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def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
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override def monitor(bundle: TLBundle, edge: TLEdgeIn) {
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val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
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monitor.io.in := TLBundleSnoop(bundle, bundle)
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}
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override def mixO(pd: TLClientPortParameters, node: OutwardNode[TLClientPortParameters, TLManagerPortParameters, TLBundle]): TLClientPortParameters =
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pd.copy(clients = pd.clients.map { c => c.copy (nodePath = node +: c.nodePath) })
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override def mixI(pu: TLManagerPortParameters, node: InwardNode[TLClientPortParameters, TLManagerPortParameters, TLBundle]): TLManagerPortParameters =
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pu.copy(managers = pu.managers.map { m => m.copy (nodePath = node +: m.nodePath) })
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}
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case class TLClientNode(portParams: Seq[TLClientPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams)
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case class TLManagerNode(portParams: Seq[TLManagerPortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams)
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case class TLAdapterNode(
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clientFn: TLClientPortParameters => TLClientPortParameters = { s => s },
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managerFn: TLManagerPortParameters => TLManagerPortParameters = { s => s })(
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implicit valName: ValName)
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extends AdapterNode(TLImp)(clientFn, managerFn)
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case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)()
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case class TLNexusNode(
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clientFn: Seq[TLClientPortParameters] => TLClientPortParameters,
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managerFn: Seq[TLManagerPortParameters] => TLManagerPortParameters)(
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implicit valName: ValName)
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extends NexusNode(TLImp)(clientFn, managerFn)
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abstract class TLCustomNode(implicit valName: ValName)
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extends CustomNode(TLImp)
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// Asynchronous crossings
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object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
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{
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def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
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def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
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def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.depth.toString)
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override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
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pd.copy(base = pd.base.copy(clients = pd.base.clients.map { c => c.copy (nodePath = node +: c.nodePath) }))
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override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
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pu.copy(base = pu.base.copy(managers = pu.base.managers.map { m => m.copy (nodePath = node +: m.nodePath) }))
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}
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case class TLAsyncAdapterNode(
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clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
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managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
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implicit valName: ValName)
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extends AdapterNode(TLAsyncImp)(clientFn, managerFn)
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case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)()
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case class TLAsyncSourceNode(sync: Int)(implicit valName: ValName)
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extends MixedAdapterNode(TLImp, TLAsyncImp)(
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dFn = { p => TLAsyncClientPortParameters(p) },
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uFn = { p => p.base.copy(minLatency = sync+1) }) // discard cycles in other clock domain
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case class TLAsyncSinkNode(depth: Int, sync: Int)(implicit valName: ValName)
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extends MixedAdapterNode(TLAsyncImp, TLImp)(
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dFn = { p => p.base.copy(minLatency = sync+1) },
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uFn = { p => TLAsyncManagerPortParameters(depth, p) })
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// Rationally related crossings
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object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
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{
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def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
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def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
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def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
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override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
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pd.copy(base = pd.base.copy(clients = pd.base.clients.map { c => c.copy (nodePath = node +: c.nodePath) }))
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override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
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pu.copy(base = pu.base.copy(managers = pu.base.managers.map { m => m.copy (nodePath = node +: m.nodePath) }))
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}
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case class TLRationalAdapterNode(
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clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
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managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
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implicit valName: ValName)
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extends AdapterNode(TLRationalImp)(clientFn, managerFn)
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case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)()
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case class TLRationalSourceNode()(implicit valName: ValName)
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extends MixedAdapterNode(TLImp, TLRationalImp)(
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dFn = { p => TLRationalClientPortParameters(p) },
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uFn = { p => p.base.copy(minLatency = 1) }) // discard cycles from other clock domain
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case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
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extends MixedAdapterNode(TLRationalImp, TLImp)(
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dFn = { p => p.base.copy(minLatency = 1) },
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uFn = { p => TLRationalManagerPortParameters(direction, p) })
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