69 lines
2.2 KiB
Scala
69 lines
2.2 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.tilelink
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import Chisel._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.util.AsyncBundle
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// READ the comments in the TLIsolation object before you instantiate this module
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class TLIsolation(fOut: (Bool, UInt) => UInt, fIn: (Bool, UInt) => UInt)(implicit p: Parameters) extends LazyModule
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{
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val node = TLAsyncAdapterNode()
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lazy val module = new LazyModuleImp(this) {
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val io = IO(new Bundle {
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val iso_out = Bool(INPUT) // Isolate from client to manager
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val iso_in = Bool(INPUT) // Isolate from manager to client
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})
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def ISOo[T <: Data](x: T): T = x.fromBits(fOut(io.iso_out, x.asUInt))
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def ISOi[T <: Data](x: T): T = x.fromBits(fIn (io.iso_in, x.asUInt))
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def ABo[T <: Data](x: AsyncBundle[T], y: AsyncBundle[T]) {
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x.mem := ISOo(y.mem)
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x.widx := ISOo(y.widx)
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x.widx_valid := ISOo(y.widx_valid)
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x.source_reset_n := ISOo(y.source_reset_n)
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y.ridx := ISOi(x.ridx)
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y.ridx_valid := ISOi(x.ridx_valid)
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y.sink_reset_n := ISOi(x.sink_reset_n)
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}
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def ABi[T <: Data](x: AsyncBundle[T], y: AsyncBundle[T]) {
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x.mem := ISOi(y.mem)
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x.widx := ISOi(y.widx)
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x.widx_valid := ISOi(y.widx_valid)
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x.source_reset_n := ISOi(y.source_reset_n)
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y.ridx := ISOo(x.ridx)
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y.ridx_valid := ISOo(x.ridx_valid)
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y.sink_reset_n := ISOo(x.sink_reset_n)
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}
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def ABz[T <: Data](x: AsyncBundle[T], y: AsyncBundle[T]) {
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x.widx := UInt(0)
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x.widx_valid := Bool(false)
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x.source_reset_n := Bool(false)
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y.ridx := UInt(0)
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y.ridx_valid := Bool(false)
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y.sink_reset_n := Bool(false)
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}
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(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
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ABo(out.a, in .a)
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ABi(in .d, out.d)
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if (edgeOut.manager.base.anySupportAcquireB && edgeOut.client.base.anySupportProbe) {
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ABi(in .b, out.b)
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ABo(out.c, in .c)
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ABo(out.e, in .e)
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} else {
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ABz(in .b, out.b)
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ABz(out.c, in .c)
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ABz(out.e, in .e)
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}
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}
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}
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}
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